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Details, datasheet, quote on part number:SN74CBT3345DBQR
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Datasheet text preview:
SN74CBT3345 8-BIT FET BUS SWITCH
SCDS027H MAY 1995 REVISED JUNE 2002
D D D
Standard '245-Type Pinout 5- Switch Connection Between Two Ports TTL-Compatible Input Levels
DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
description
The SN74CBT3345 provides eight bits of high-speed TTL-compatible bus switching in a standard '245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as one 8-bit switch bank with dual output-enable (OE and OE) inputs. When OE is low or OE is high, the switch is on, and port A is connected to port B. When OE is high and OE is low, the switch is open, and the high-impedance state exists between the two ports. ORDERING INFORMATION
TA SOIC DW DW 40°C to 85°C to 85°C SSOP DB SSOP (QSOP) DBQ TSSOP PW PACKAGE Tube Tape and reel Tape and reel Tape and reel Tape and reel
OE A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
ORDERABLE PART NUMBER SN74CBT3345DW SN74CBT3345DWR SN74CBT3345DBR SN74CBT3345DBQR SN74CBT3345PWR
TOP-SIDE MARKING CBT3345 CU345 CBT3345 CU345
TVSOP DGV Tape and reel SN74CBT3345DGVR CU345 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE H X L OE X L H FUNCTION A port = B port A port = B port Disconnect
logic diagram (positive logic)
2 A1 18 B1
A8 OE OE
9 1 19
11
B8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74CBT3345 8-BIT FET BUS SWITCH
SCDS027H MAY 1995 REVISED JUNE 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4.5 2 0.8 85 MAX 5.5 UNIT V V V °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC ICC§ Ci Cio(OFF) ron¶ All inputs Control inputs Control inputs VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, VI = VCC or GND Other inputs at VCC or GND 3 OE = VCC or OE = GND VI = 0 VI = 2.4 V, II = 64 mA II = 30 mA II = 15 mA 6 5 5 10 7 7 15 MIN TYP MAX 1.2 ±1 50 3.5 UNIT V µA µA mA pF pF
All typical values are at VCC = 5 V, TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBT3345 8-BIT FET BUS SWITCH
SCDS027H MAY 1995 REVISED JUNE 2002
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten FROM (INPUT) A or B OE or OE TO (OUTPUT) B or A A or B 1 VCC = 5 V ± 0.5 V MIN MAX 0.25 9.1 ns ns UNIT
tdis A or B 1 8.7 ns OE or OE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
3V LOAD CIRCUIT Output Control 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 1 S1 at 7 V (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B) 1.5 V tPLZ 3.5 V VOL + 0.3 V VOL tPHZ VOH VOH 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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