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Details, datasheet, quote on part number:SN74CBTD3384CPW
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Datasheet text preview:
SN74CBTD3384C 10 BIT FET BUS SWITCH WITH LEVEL SHIFTING 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS133A -SEPTEMBER 2003 - REVISED OCTOBER 2003
D Undershoot Protection for Off-Isolation on D D D D D D
A and B Ports Up To -2 V Integrated Diode to VCC Provides 5-V Input Down To 3.3-V Output Level Shift Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes VCC Operating Range From 4.5 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels D D D D
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating
D
DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE
description/ordering information
ORDERING INFORMATION
TA SOIC - DW SSOP - DB -40°C to 85°C SSOP (QSOP) - DBQ TSSOP - PW PACKAGE Tube Tape and reel Tube Tape and reel Tape and reel Tube Tape and reel ORDERABLE PART NUMBER SN74CBTD3384CDW SN74CBTD3384CDWR SN74CBTD3384CDB SN74CBTD3384CDBR SN74CBTD3384CDBQR SN74CBTD3384CPW SN74CBTD3384CPWR CC384C CC384C CBTD3384C CBTD3384C TOP-SIDE MARKING
TVSOP - DGV Tape and reel SN74CBTD3384CDGVR CC384C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SCDS133A -SEPTEMBER 2003 - REVISED OCTOBER 2003
SN74CBTD3384C 10 BIT FET BUS SWITCH WITH LEVEL SHIFTING 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
description/ordering information (continued)
The SN74CBTD3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. This device features an integrated diode in series with VCC to provide level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3384C provides protection for undershoot up to -2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBTD3384C is organized as two 5-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE (each 5-bit bus switch) INPUT OE L H INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect
logic diagram (positive logic)
3 1A1 SW 2 1B1
11 1A5 SW
10 1B5
1 1OE
14 2A1 SW
15 2B1
22 2A5 SW
23 2B5
13 2OE
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBTD3384C 10 BIT FET BUS SWITCH WITH LEVEL SHIFTING 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS133A -SEPTEMBER 2003 - REVISED OCTOBER 2003
simplified schematic, each FET switch (SW)
A B
Undershoot Protection Circuit
EN EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 6 and 7)
MIN VCC VIH VIL VI/O Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage 4.5 2 0 0 MAX 5.5 5.5 0.8 5.5 UNIT V V V V
TA Operating free-air temperature -40 85 °C NOTES: 6. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7. In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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