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Details, datasheet, quote on part number:SN74CBTD3861DBR
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Datasheet text preview:
SN74CBTD3861 10-BIT FET BUS SWITCH WITH LEVEL SHIFTING
SCDS084G JULY 1998 REVISED JULY 2002
D D D
5- Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications
DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
description/ordering information
The SN74CBTD3861 provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. A diode to VCC is integrated on the die to allow for level shifting from 5-V signals at the device inputs to 3.3-V signals at the device outputs. The device is organized as one 10-bit switch with a single output-enable (OE) input. When OE is low, the switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. ORDERING INFORMATION
TA SOIC DW DW 40°C to 85°C to 85°C SSOP DB SSOP (QSOP) DBQ TSSOP PW PACKAGE Tube Tape and reel Tape and reel Tape and reel Tape and reel
NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC OE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
NC No internal connection
ORDERABLE PART NUMBER SN74CBTD3861DW SN74CBTD3861DWR SN74CBTD3861DBR SN74CBTD3861DBQR SN74CBTD3861PWR
TOP-SIDE MARKING CBTD3861 CC861 CBTD3861 CC861
TVSOP DGV Tape and reel SN74CBTD3861DGVR CC861 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUT OE L H FUNCTION A port = B port Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74CBTD3861 10-BIT FET BUS SWITCH WITH LEVEL SHIFTING
SCDS084G JULY 1998 REVISED JULY 2002
logic diagram (positive logic)
2 A1 22 B1
11 A10
13 B10
OE
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4.5 2 0.8 85 MAX 5.5 UNIT V V V °C
In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect. NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBTD3861 10-BIT FET BUS SWITCH WITH LEVEL SHIFTING
SCDS084G JULY 1998 REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH II ICC ICC Ci Control inputs Control inputs VCC = 4.5 V, See Figure 2 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, OE = VCC VI = 0 II = 64 mA II = 30 mA MIN TYP MAX 1.2 ±1 VI = VCC or GND Other inputs at VCC or GND 2.5 4 5 5 7 7 1.5 2.5 UNIT V µA mA mA pF pF
Cio(OFF) ron§
VI = 2.4 V, II = 15 mA 20 50 All typical values are at VCC = 5 V, TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER tpd¶ ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B 2.6 MIN MAX 0.35 10 UNIT ns ns
tdis A or B 1 6 ns OE ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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