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Details, datasheet, quote on part number:SN74CBTH16211DGGR
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Datasheet text preview:
SN74CBTH16211 24-BIT FET BUS SWITCH WITH BUS HOLD
SCDS062C JUNE 1998 REVISED NOVEMBER 2001
D D D
5- Switch Connection Between Two Ports TTL-Compatible Input Levels Bus Hold on Data Inputs/Outputs Eliminates the Need for External Pullup/Pulldown Resistors
DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
The SN74CBTH16211 provides 24 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as dual 12-bit bus switches with separate output-enable (OE) inputs. It can be used as two 12-bit bus switches or one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is on, and the A port is connected to the B port. When OE is high, the switch is open, and a high-impedance state exists between the two ports. Active bus-hold circuitry is provided to hold unused or floating A and B ports at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12
NC No internal connection
ORDERING INFORMATION
TA PACKAGE SSOP DL DL 40°C to 85°C to 85°C TSSOP DGG TVSOP DGV Tube Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CBTH16211DL SN74CBTH16211DLR SN74CBTH16211DGGR SN74CBTH16211DGVR TOP-SIDE MARKING CBTH16211 CBTH16211 CYH211
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74CBTH16211 24-BIT FET BUS SWITCH WITH BUS HOLD
SCDS062C JUNE 1998 REVISED NOVEMBER 2001
FUNCTION TABLE (each bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
logic diagram (positive logic)
2 1A1 14 1A12 54 1B1 42 1B12
56 1OE 15 2A1 41 2B1
28 2A12
29 2B12
55 2OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4 2 0.8 85 MAX 5.5 UNIT V V V °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBTH16211 24-BIT FET BUS SWITCH WITH BUS HOLD
SCDS062C JUNE 1998 REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II IBHL IBHH§ IBHLO¶ IBHHO# ICC ICC|| Control inputs Control inputs All inputs VCC = 4.5 V, VCC = 0 V, VCC = 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 4 V, TYP at VCC = 4 V VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V VI = 5.5 V or GND VI = 0.8 V VI = 2 V VI = 0 to 5.5 V VI = 0 to 5.5 V IO = 0, One input at 3.4 V, VI = 2.4 V, VI = 0 VI = VCC or GND Other inputs at VCC or GND II = 15 mA II = 64 mA II = 30 mA 14 5 5 100 100 500 500 3 2.5 20 7 7 MIN TYP MAX 1.2 ±10 ±10 UNIT V µA µA µA µA µA µA mA
ronk
VI = 2.4 V, II = 15 mA 8 12 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. k Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpdh ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 4 V MIN MAX 0.35 9.9 9.5 1 1 VCC = 5 V ± 0.5 V MIN MAX 0.25 9.6 8.3 ns ns ns UNIT
h The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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