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Details, datasheet, quote on part number:SN74CBTLV3861DGVR
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Datasheet text preview:
SN74CBTLV3861 LOW VOLTAGE 10 BIT FET BUS SWITCH
SCDS041H - DECEMBER 1997 - REVISED OCTOBER 2003
D 5- Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports D Ioff Supports Partial-Power-Down Mode D D
Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
The SN74CBTLV3861 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as one 10-bit bus switch. When output enable (OE) is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.
NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC OE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
NC - No internal connection
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE QSOP - DBQ SOIC - DW -40°C to 85°C SOP - NS TSSOP - PW TVSOP - DGV Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CBTLV3861DBQR SN74CBTLV3861DW SN74CBTLV3861DWR SN74CBTLV3861NSR SN74CBTLV3861PWR SN74CBTLV3861DGVR CBTLV3861 CBTLV3861 CL861 TOP-SIDE MARKING CL861
CL861 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUT OE L H FUNCTION A port = B port Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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· DALLAS, TEXAS 75265
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SN74CBTLV3861 LOW VOLTAGE 10 BIT FET BUS SWITCH
SCDS041H - DECEMBER 1997 - REVISED OCTOBER 2003
logic diagram (positive logic)
2 A1 SW 22 B1
11 A10 SW
13 B10
23 OE
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBTLV3861 LOW VOLTAGE 10 BIT FET BUS SWITCH
SCDS041H - DECEMBER 1997 - REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
MIN VCC VIH VIL Supply voltage High-level control input voltage Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0.7 0.8 V V MAX 3.6 UNIT V
TA Operating free-air temperature -40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II Ioff ICC ICC Ci Control inputs Control inputs VCC = 3 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, VCC = 3.6 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 2.3 V, TYP at VCC = 2.5 V ron§ VCC = 3 V TEST CONDITIONS II = -18 mA VI = VCC or GND VI or VO = 0 to 3.6 V IO = 0, One input at 3 V, OE = VCC VI = 0 VI = 1.7 V, VI = 0 II = 64 mA II = 24 mA II = 15 mA II = 64 mA VI = VCC or GND Other inputs at VCC or GND 3 5 5 5 27 5 8 8 40 7 MIN TYP MAX -1.2 ±1 10 10 300 UNIT V µA µA µA µA pF pF
Cio(OFF)
II = 24 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER tpd¶ ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B 2.1 1.7 VCC = 2.5 V ± 0.2 V MIN MAX 0.15 5.5 5.5 2.1 2.5 VCC = 3.3 V ± 0.3 V MIN MAX 0.25 4.9 5.8 ns ns ns UNIT
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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