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Details, datasheet, quote on part number:SN74F574DWR
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| Part: | SN74F574DWR |
| Category: | Logic => Flip-Flops => D-Type (3-State) Flip-Flops |
| Description: | ti SN74F574, Octal Edge-triggered D-type Flip-flops With 3-State Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74F574DWR datasheet File size : 71 kB |
| Request For quote: | Find where to buy SN74F574DWR
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Datasheet text preview:
SN74F574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SDFS005A D3034, SEPTEMBER 1987 REVISED OCTOBER 1993
· · · · ·
Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VC C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F574 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK L X D H L X X OUTPUT Q H L Q0 Z
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
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SN74F574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SDFS005A D3034, SEPTEMBER 1987 REVISED OCTOBER 1993
logic symbol
OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 3 4 5 6 7 8 9 EN C1 1D 19 18 17 16 15 14 13 12
logic diagram (positive logic)
OE CLK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q To Seven Other Channels 1D 2 C1 1D 19 1Q 1 11
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.
recommended operating conditions
MIN VCC VIH VIL IIK IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature 0 4.5 2 0.8 18 3 24 70 NOM 5 MAX 5.5 UNIT V V V mA mA mA °C
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74F574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SDFS005A D3034, SEPTEMBER 1987 REVISED OCTOBER 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IOS ICCZ VCC = 4.5 V, VCC = 4 5 V 4.5 VCC = 4.75 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = 18 mA IOH = 1 mA IOH = 3 mA IOH = 1 mA to 3 mA IOL = 24 mA VO = 2.7 V VO = 0.5 V VI = 7 V VI = 2.7 V VI = 0.5 V VO = 0 See Note 2 60 MIN 2.5 2.4 2.7 0.35 0.5 50 50 0.1 20 0.6 150 86 V µA µA mA µA mA mA mA TYP 3.4 3.3 V MAX 1.2 UNIT V
VCC = 5.5 V, 55 All typical values are at VCC = 5 V, TA = 25°C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICCZ is measured with OE at 4.5 V and all other inputs grounded.
timing requirements
VCC = 5 V, TA = 25°C MIN fclock tw tsu th Clock frequency Pulse duration duration Setup time before CLK time before CLK Hold time after CLK time after CLK CLK high CLK low Data high Data low Data high Data low 0 7 6 2 2 2 2 MAX 100 VCC = 4.5 V to 5.5 V, TA = MIN to MAX§ MIN 0 7 6 2 2 2 2 MAX 100 MHz ns ns ns UNIT
switching characteristics (see Note 3)
FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 , TA = 25°C MIN fmax tPLH tPHL tPZH tPZL tPHZ 100 CLK Any Q Any Q 3.2 3.2 1.2 1.2 6.1 6.1 8.6 4.9 8.5 8.5 11.5 7.5 TYP MAX VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX § MIN 100 3.2 3.2 1.2 1.2 10 10 12.5 8.5 8 6.5 MAX MHz ns ns ns
PARAMETER
UNIT
OE
1.2 4.9 7 1.2 OE Any Q tPLZ 1.2 3.9 5.5 1.2 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
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