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Details, datasheet, quote on part number:SN74F657
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| Part: | SN74F657 |
| Category: | Logic => Bus Interface => Bus Oriented Circuits |
| Description: | Octal Bus Transceiver With Parity Generator/checker And 3-state Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74F657 datasheet File size : 114 kB |
| Request For quote: | Find where to buy SN74F657
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Datasheet text preview:
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A D3217, JANUARY 1989 REVISED OCTOBER 1993
· · · · · ·
Combines F245 and F280B Functions in One Package High-Impedance N-P-N Inputs for Reduced Loading (70 µA in Low and High States) High Output Drive and Light Bus Loading 3-State B Outputs Sink 64 mA and Source 15 mA Input Diodes for Termination Effects Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR NT PACKAGE (TOP VIEW)
description
The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.
T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY
The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port from the B port. When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R low), PARITY is an input. When transmitting (T/R high), the parity select (ODD/EVEN) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity. When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN is low (for even parity) and the number of highs on B port is: 1. Odd and the PARITY input is high, then ERR will be high signifying no error. 2. Even and the PARITY input is high, then ERR will be low indicating an error. The SN74F657 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A D3217, JANUARY 1989 REVISED OCTOBER 1993
FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH INPUTS OE L L 0, 2, 4, 6, 8 246 L L L L L L 1, 3 5 7 3, 5, L L L L Don't care H T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X INPUT/OUTPUT PARITY H L H L H L L H H L H L Z OUTPUTS ERR Z Z H L L H Z Z L H H L Z OUTPUT MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z
logic symbol
OE T/R ODD/EVEN A1 A2 A3 A4 A5 A6 A7 A8 24 1 11 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 2k 4, 2 5 4, 1 12 ERR G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 1 Z11 1 2 23 B1
22 21 20 17 16 15 14
B2 B3 B4 B5 B6 B7 B8
13
PARITY
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A D3217, JANUARY 1989 REVISED OCTOBER 1993
logic diagram (positive logic)
T/R 1
OE A1
24 2 3
23 22
B1
A2
B2
A3
4
21
B3
A4
5
20
B4
A5
6
17
B5
A6
8
16
B6
A7
9
15
B7
A8
10
14
B8
ODD/EVEN
11
13 12
PARITY ERR
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
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