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Details, datasheet, quote on part number:SN74F74D
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| Part: | SN74F74D |
| Category: | Logic => Flip-Flops => D-Type Flip-Flops |
| Description: | ti SN74F74, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74F74D datasheet File size : 78 kB |
| Request For quote: | Find where to buy SN74F74D
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Datasheet text preview:
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
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Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
SN54F74 . . . J PACKAGE SN74F74 . . . D OR N PACKAGE (TOP VIEW)
description
These devices contain two independent positiveedge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The SN54F74 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS PRE L H L H H H CLR H L L H H H CLK X X X L D X X X H L X OUTPUTS Q H L H H L Q0 Q L H H L H Q0
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
SN54F74 . . . FK PACKAGE (TOP VIEW)
1CLK NC 1PRE NC 1Q
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1D 1CLR NC VCC 2CLR 2D NC 2CLK NC 2PRE
NC No internal connection
Copyright © 1993, Texas Instruments Incorporated
The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1Q GND NC 2Q 2Q
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SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
logic symbol
1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 3 2 1 10 11 12 8 13 2Q S C1 1D R 9 6 1Q 5 1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
logic diagram, each flip-flop (positive logic)
PRE CLK C C Q TG C C C D TG TG TG C C
Q C CLR C C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range: SN54F74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74F74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
recommended operating conditions
SN54F74 MIN VCC VIH VIL IIK IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.8 18 1 20 125 0 NOM 5 MAX 5.5 MIN 4.5 2 0.8 18 1 20 70 SN74F74 NOM 5 MAX 5.5 UNIT V V V mA mA mA °C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL Data, CLK PRE or CLR VCC = 4.5 V, VCC = 4.5 V, VCC = 4.75 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 V, TEST CONDITIONS CONDITIONS II = 18 mA IOH = 1 mA IOH = 1 mA IOL = 20 mA VI = 7 V VI = 2.7 V VI = 0 5 V 0.5 MIN 2.5 SN54F74 TYP MAX 1.2 3.4 0.3 0.5 0.1 20 0.6 1.8 2.5 2.7 0.3 0.5 0.1 20 0.6 1.8 150 16 3.4 MIN SN74F74 TYP MAX 1.2 UNIT V V V mA µA mA mA mA
IOS VCC = 5.5 V, VO = 0 60 150 60 ICC VCC = 5.5 V, See Note 2 10.5 16 10.5 All typical values are at VCC = 5 V, TA = 25°C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with D, CLK, and PRE grounded then with D, CLK, and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 5 V, TA = 25°C F74 MIN fclock tw Clock frequency Pulse duration duration Setup time, data before CLK time data before CLK Setup time, inactive-state before CLK§ th Hold time data after CLK time, data after CLK CLK high, PRE or CLR low CLK low High Low PRE or CLR to CLK High Low 0 4 5 2 3 2 1 1 MAX 100 MIN 0 4 6 3 4 3 2 2 MAX 80 MIN 0 4 5 2 3 2 1 1 ns ns MAX 100 MHz ns SN54F74 SN74F74
UNIT
tsu
§ Inactive-state setup time is also referred to as recovery time.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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