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Details, datasheet, quote on part number:SN74HC163DR
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Datasheet text preview:
SN54HC163, SN74HC163 4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS298D - JANUARY 1996 - REVISED - OCTOBER 2003
D D D D D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable
SN54HC163 . . . J OR W PACKAGE SN74HC163 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RCO QA QB QC QD ENT LOAD
description/ordering information
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The 'HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W Reel of 2000 Reel of 250 Tube of 25 Tube of 150
SN54HC163 . . . FK PACKAGE (TOP VIEW)
A B NC C D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLK CLR NC VCC RCO QA QB NC QC QD
NC - No internal connection ORDERABLE PART NUMBER SN74HC163N SN74HC163D SN74HC163DR SN74HC163DT SN74HC163NSR SN74HC163DBR SN74HC163PW SN74HC163PWR SN74HC163PWT SNJ54HC163J SNJ54HC163W SNJ54HC163J SNJ54HC163W HC163 HC163 HC163 HC163
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
LCCC - FK Tube of 55 SNJ54HC163FK SNJ54HC163FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
ENP GND NC LOAD ENT
TOP-SIDE MARKING SN74HC163N
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SN54HC163, SN74HC163 4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS298D - JANUARY 1996 - REVISED - OCTOBER 2003
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the 'HC163 devices is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC163, SN74HC163 4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS298D - JANUARY 1996 - REVISED - OCTOBER 2003
logic diagram (positive logic)
LOAD ENT ENP 9 10 7 LD CK CLK CLR 2 1 CK R LD 15
RCO
A
3
M1 G2 1, 2T/1C3 G4 3D 4R M1 G2 1, 2T/1C3 G4 3D 4R
14
QA
13
QB
B
4
C
5
M1 G2 1, 2T/1C3 G4 3D 4R
12
QC
D
6
M1 G2 1, 2T/1C3 G4 3D 4R
11
QD
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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