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Details, datasheet, quote on part number:SN74HC259NSR
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Datasheet text preview:
SN54HC259, SN74HC259 8 BIT ADDRESSABLE LATCHES
SCLS134E - DECEMBER 1982 - REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V D High-Current Inverting Outputs Drive Up To D D D D D D D D D D
10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes
SN54HC259 . . . J OR W PACKAGE SN74HC259 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
S0 S1 S2 Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC CLR G D Q7 Q6 Q5 Q4
SN54HC259 . . . FK PACKAGE (TOP VIEW)
description/ordering information
These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85 C 85°C SOP - NS TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Reel of 250 Tube of 25 Tube of 150
S2 Q0 NC Q1 Q2
S1 S0 NC VCC CLR
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13
G D NC Q7 Q6
NC - No internal connection
ORDERABLE PART NUMBER SN74HC259N SN74HC259D SN74HC259DR SN74HC259DT SN74HC259NSR SN74HC259PWR SN74HC259PWT SNJ54HC259J SNJ54HC259W
LCCC - FK Tube of 55 SNJ54HC259FK SNJ54HC259FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Q3 GND NC Q4 Q5
TOP-SIDE MARKING SN74HC259N HC259 HC259 HC259 SNJ54HC259J SNJ54HC259W
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SN54HC259, SN74HC259 8 BIT ADDRESSABLE LATCHES
SCLS134E - DECEMBER 1982 - REVISED SEPTEMBER 2003
description/ordering information (continued)
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. Function Tables
FUNCTION INPUTS CLR H H L L G L H L H OUTPUT OF ADDRESSED LATCH D QiO D L EACH OTHER OUTPUT QiO QiO L L FUNCTION Addressable latch Memory 8-line demultiplexer Clear
LATCH SELECTION SELECT INPUTS S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H LATCH ADDRESSED 0 1 2 3 4 5 6 7
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC259, SN74HC259 8 BIT ADDRESSABLE LATCHES
SCLS134E - DECEMBER 1982 - REVISED SEPTEMBER 2003
logic diagram
S0 1 D C R D C R D C R D C R S2 3 D C R D C R G 14 D C R D 13 D C R CLR 15 Q 12 Q7 Q 11 Q6 Q 9 4
Q
Q0
Q
5
Q1
S1
2
Q
6
Q2
Q
7
Q3
Q4
Q
10
Q5
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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