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Details, datasheet, quote on part number:SN74HC259PW
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Datasheet text preview:
SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES
SCLS134B DECEMBER 1982 REVISED MAY 1997
D D D D D D D
8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HC259 . . . J OR W PACKAGE SN74HC259 . . . D, N, OR PW PACKAGE (TOP VIEW)
S0 S1 S2 Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC CLR G D Q7 Q6 Q5 Q4
SN54HC259 . . . FK PACKAGE (TOP VIEW)
description
These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
S2 Q0 NC Q1 Q2
4 5 6 7 8
S1 S0 NC VCC CLR
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
G D NC Q7 Q6
NC No internal connection
The SN54HC259 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HC259 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Q3 GND NC Q4 Q5
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SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES
SCLS134B DECEMBER 1982 REVISED MAY 1997
Function Tables
FUNCTION INPUTS CLR H H L L G L H L H OUTPUT OF ADDRESSED LATCH D QiO D L EACH OTHER OUTPUT QiO QiO L L FUNCTION Addressable latch Memory 8-line demultiplexer Clear
LATCH SELECTION SELECT INPUTS S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H LATCH ADDRESSED 0 1 2 3 4 5 6 7
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES
SCLS134B DECEMBER 1982 REVISED MAY 1997
logic symbol
S0 S1 S2 G D CLR 1 2 3 14 13 15 8M 2 G8 Z9 Z10 9, 0D 10, 0R 9, 1D 10, 1R 9, 2D 10, 2R 9, 3D 10, 3R 9, 4D 10, 4R 9, 5D 10, 5R 9, 6D 10, 6R 9, 7D 10, 7R This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages. 12 11 10 9 7 6 5 4 0 0 7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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