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Part: SN74HCT273PWR
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti SN74HCT273, Octal D-type Flip-flops With Clear
Company: Texas Instruments, Inc.
Datasheet: Download SN74HCT273PWR datasheet File size : 81 kB
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Datasheet text preview:
SCLS068E - NOVEMBER 1988 - REVISED AUGUST 2003
SN54HCT273, SN74HCT273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
D D D D D D
Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max
SN54HCT273 . . . J OR W PACKAGE SN74HCT273 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
D D D D
Inputs Are TTL-Voltage Compatible Contain Eight D-Type Flip-Flops Direct Clear Input Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators
SN54HCT273 . . . FK PACKAGE (TOP VIEW)
1D 1Q C LR VCC 2D 2Q 3Q 3D 4D
CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
description/ordering information
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The 'HCT273 devices are similar to the 'HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLR. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85°C SOP - NS SSOP - DB PACKAGE Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 70 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 20 Tube of 85 Tube of 55 ORDERABLE PART NUMBER SN74HCT273N SN74HCT273DW SN74HCT273DWR SN74HCT273NSR SN74HCT273DBR SN74HCT273PW SN74HCT273PWR SN74HCT273PWT SNJ54HCT273J SNJ54HCT273W SNJ54HCT273FK SNJ54HCT273J SNJ54HCT273W HT273 HCT273 HCT273 HT273 TOP-SIDE MARKING SN74HCT273N
SNJ54HCT273FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
4Q GND CLK 5Q 5D
Copyright 2003, Texas Instruments Incorporated
1
SCLS068E - NOVEMBER 1988 - REVISED AUGUST 2003
SN54HCT273, SN74HCT273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUT Q L H L Q0
logic diagram (positive logic)
1D CLK 11 3 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18
1D C1 R CLR 1 2 1Q
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
5 2Q
6 3Q
9 4Q
12 5Q
15 6Q
16 7Q
19 8Q
logic diagram, each flip-flop (positive logic)
C C
D
TG C C TG
TG
Q C
C
CLK(I)
C C C
TG
C R
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SCLS068E - NOVEMBER 1988 - REVISED AUGUST 2003
SN54HCT273, SN74HCT273 OCTAL D TYPE FLIP FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT273 MIN VCC VIH VIL VI VO t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT273 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II ICC ICC Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = -20 µA IOH = -4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 TA = 25°C MIN TYP MAX 4.4 3.98 4.499 4.30 0.001 0.17 ±0.1 0.1 0.26 ±100 8 2.4 10 SN54HCT273 MIN 4.4 3.7 0.1 0.4 ±1000 160 3 10 MAX SN74HCT273 MIN 4.4 3.84 0.1 0.33 ±1000 80 2.9 10 V nA µA mA pF V MAX UNIT
IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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