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Details, datasheet, quote on part number:SN74HCT373PWT
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Datasheet text preview:
SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS009D MARCH 1984 REVISED AUGUST 2003
D D D D D D D D D
Operating Voltage Range of 4.5 V to 5.5 V High-Current 3-State True Outputs Can Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package Full Parallel Access for Loading
SN54HCT373 . . .J OR W PACKAGE SN74HCT373 . . .DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 'HCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. ORDERING INFORMATION
TA PDIP N SOIC DW 85°C 40°C to 85 C SOP NS SSOP DB TSSOP PW CDIP J 125°C 55°C to 125 C CFP W LCCC FK PACKAGE Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 70 Reel of 2000 Reel of 250 Tube of 20 Tube of 85 Tube of 55 ORDERABLE PART NUMBER SN74HCT373N SN74HCT373DW SN74HCT373DWR SN74HCT373NSR SN74HCT373DBR SN74HCT373PW SN74HCT373PWR SN74HCT373PWT SNJ54HCT373J SNJ54HCT373W SNJ54HCT373FK SNJ54HCT373J SNJ54HCT373W HT373 TOP-SIDE MARKING SN74HCT373N HCT373 HCT373 HT373 SN54HCT373 . . .FK PACKAGE (TOP VIEW)
1D 1Q OE VCC 8Q 2D 2Q 3Q 3D 4D
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8D 7D 7Q 6Q 6D
SNJ54HCT373FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
4Q GND LE 5Q 5D
1
SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS009D MARCH 1984 REVISED AUGUST 2003
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE 1
LE
11 C1 2
1D
3
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS009D MARCH 1984 REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HCT373 MIN VCC VIH VIL VI VO t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT373 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC IOH = 20 µA IOH = 6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT373 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT373 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 MAX UNIT V V nA µA µA mA pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V TA = 25°C MIN MAX 20 17 10 9 10 10 SN54HCT373 MIN 30 27 15 14 10 10 MAX SN74HCT373 MIN 25 23 13 12 10 10 MAX UNIT ns ns ns
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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