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Part: SN74LV161284DGGR
Category:
Logic
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Description: ti SN74LV161284, 19-Bit Bus Interface
Company: Texas Instruments, Inc.
Datasheet: Download SN74LV161284DGGR datasheet File size : 214 kB
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Datasheet text preview:
SN74LV161284 19-BIT BUS INTERFACE
SCLS426C OCTOBER 1998 REVISED NOVEMBER 2002
D D D D D D
4.5-V to 5.5-V VCC Operation 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JEDEC 17 ESD Protection Exceeds JESD 22 4000-V Human-Body Model (A114-A) 300-V Machine Model (A115-A) 2000-V Charged-Device Model (C101)
DGG OR DL PACKAGE (TOP VIEW)
description/ordering information
The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
HD A9 A10 A11 A12 A13 VCC A1 A2 GND A3 A4 A5 A6 GND A7 A8 VCC PERI LOGIC IN A14 A15 A16 A17 HOST LOGIC OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DIR Y9 Y10 Y11 Y12 Y13 VCC CABLE B1 B2 GND B3 B4 B5 B6 GND B7 B8 VCC CABLE PERI LOGIC OUT C14 C15 C16 C17 HOST LOGIC IN
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low. The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation. ORDERING INFORMATION
TA SSOP DL DL PACKAGE Tube Tape and reel ORDERABLE PART NUMBER SN74LV161284DL SN74LV161284DLR TOP-SIDE MARKING LV161284
40°C to 85°C
TSSOP DGG Tape and reel SN74LV161284DGGR LV161284 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
SN74LV161284 19-BIT BUS INTERFACE
SCLS426C OCTOBER 1998 REVISED NOVEMBER 2002
FUNCTION TABLE INPUTS DIR L L H H HD L H L H OUTPUT Open drain Totem pole Totem pole Open drain Totem pole Totem pole MODE A9A13 to Y9Y13 and PERI LOGIC IN to PERI LOGIC OUT B1B8 to A1A8 and C14C17 to A14A17 B1B8 to A1A8, A9A13 to Y9Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14C17 to A14A17 A1A8 to B1B8, A9A13 to Y9Y13, and PERI LOGIC IN to PERI LOGIC OUT C14C17 to A14A17 A1A8 to B1B8, A9A13 to Y9Y13, C14C17 to A14A17, and PERI LOGIC IN to PERI LOGIC OUT
logic diagram (positive logic)
VCC CABLE DIR HD 42 48 1 See Note B See Note B See Note A A1A8
B1B8 A9A13 Y9Y13
PERI LOGIC IN
19
30
PERI LOGIC OUT
A14A17 24 25
C14C17
HOST LOGIC OUT
HOST LOGIC IN
NOTES: A. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. B. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS is turned off when the associated driver is in the low state.
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POST OFFICE BOX 655303
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SN74LV161284 19-BIT BUS INTERFACE
SCLS426C OCTOBER 1998 REVISED NOVEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: VCC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . 2 V to 7 V Peripheral side (see Note 1) . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is more negative than 0.5 V. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN VCC CABLE VCC Supply voltage for the cable side, VCC CABLE VCC Supply voltage A, DIR, HD, and PERI LOGIC IN VIH High-level input voltage input voltage B C14C17 HOST LOGIC IN A, DIR, HD, and PERI LOGIC IN VIL Low-level input voltage input voltage B C14C17 HOST LOGIC IN VI VO IOH Input voltage voltage Open-drain output voltage High-level output current Peripheral side Cable side B, Y, and PERI LOGIC OUT (HD low) B and Y outputs (HD high) A outputs and HOST LOGIC OUT PERI LOGIC OUT B and Y outputs IOL Low-level output current A outputs and HOST LOGIC OUT PERI LOGIC OUT 0 0 0 4.5 4.5 VCC × 0.7 2 2.3 2.6 VCC × 0.3 0.8 0.8 1.6 VCC 5.5 5.5 14 8 0.5 14 8 84 mA mA V V MAX 5.5 5.5 UNIT V V
V
V
TA Operating free-air temperature 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
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