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Part: SN74LV163ARGYR
Category:
Logic
-> Counters
-> Binary Counters
Description: ti SN74LV163A, 4-Bit Synchronous Binary Counters
Company: Texas Instruments, Inc.
Datasheet: Download SN74LV163ARGYR datasheet File size : 214 kB
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Datasheet text preview:
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS405D APRIL 1998 REVISED JULY 2003
D D D D D D D
2-V to 5.5-V VCC Operation Max tpd of 9.5 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Internal Look Ahead for Fast Counting Carry Output for n-Bit Cascading
D D D D D
Synchronous Counting Synchronously Programmable Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LV163A . . . FK PACKAGE (TOP VIEW)
CLR
LOAD
GND
8
9
NC No internal connection
description/ordering information
ORDERING INFORMATION
TA PACKAGE QFN RGY SOIC D SOP NS 40°C to 85°C SSOP DB TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC FK Reel of 1000 Tube of 40 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74LV163ARGYR SN74LV163AD SN74LV163ADR SN74LV163ANSR SN74LV163ADBR SN74LV163APW SN74LV163APWR SN74LV163APWT SN74LV163ADGVR SNJ54LV163AJ SNJ54LV163AW SNJ54LV163AFK LV163A SNJ54LV163AJ SNJ54LV163AW LV163A TOP-SIDE MARKING LV163A LV163A 74LV163A LV163A
SNJ54LV163AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
LOAD ENT
ENP GND NC
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7
16 15 14 13 12 11 10
VCC RCO QA QB QC QD ENT LOAD
1
16 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT
CLK A B C D ENP
2 3 4 5 6 7 8 9
A B NC C D
CLK CLR NC VCC RCO
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
VCC
SN54LV163A . . . J OR W PACKAGE SN74LV163A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
SN74LV163A . . . RGY PACKAGE (TOP VIEW)
QA QB NC QC QD
1
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS405D APRIL 1998 REVISED JULY 2003
description/ordering information (continued)
The 'LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. These synchronous, presettable counters feature an internal carry look ahead for application in high-speed counting designs. The 'LV163A devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the 'LV163A devices is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE INPUTS CLR L H H H H H LOAD X L H H H X ENP X X X L H X ENT X X L X H X CLK X QA L A OUTPUTS QB L B QC L C QD L D FUNCTION Reset to "0" Preset data No count No count Count No count
No change No change Count up No change
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS405D APRIL 1998 REVISED JULY 2003
logic diagram (positive logic)
LOAD ENT ENP 9 10 7 LD CK CLK CLR 2 1 CK R LD 15
RCO
A
3
M1 G2 1, 2T/1C3 G4 3D 4R M1 G2 1, 2T/1C3 G4 3D 4R
14
QA
13
QB
B
4
C
5
M1 G2 1, 2T/1C3 G4 3D 4R
12
QC
D
6
M1 G2 1, 2T/1C3 G4 3D 4R
11
QD
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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