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Part: SN74LV164A
Category:
Logic
-> Registers
-> CMOS/BiCMOS->LV/LVQ/LVX Family->Low Voltage
Description: 8-bit Parallel-out Serial Shift Registers
Company: Texas Instruments, Inc.
Datasheet: Download SN74LV164A datasheet File size : 214 kB
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Datasheet text preview:
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403D APRIL 1998 REVISED JANUARY 2001
D D D D D D
2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
A B QA QB QC QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC QH QG QF QE CLR CLK
SN54LV164A . . . FK PACKAGE (TOP VIEW)
description
The 'LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation. These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. ORDERING INFORMATION
TA SOIC D 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC - FK PACKAGE Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74LV164AD SN74LV164ADR SN74LV164ANSR SN74LV164ADBR SN74LV164APWR SN74LV164ADGVR SNJ54LV164AJ SNJ54LV164AW SNJ54LV164AFK
B A NC VCC QH QA NC QB NC QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
QG NC QF NC QE
NC No internal connection
SNJ54LV164AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC CLK CLR
TOP-SIDE MARKING LV164A 74LV164A LV164A LV164A LV164A SNJ54LV164AJ SNJ54LV164AW
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SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403D APRIL 1998 REVISED JANUARY 2001
FUNCTION TABLE INPUTS CLR L H H H H CLK X L A X X H L X B X X H X L QA L QA0 H L L OUTPUTS QB . . . QH L QB0 QAn QAn QAn L Q H0 QGn QGn QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = the level of QA or QG before the most recent transition of the clock: indicates a 1-bit shift
logic symbol
CLR CLK 9 8 SRG8 R C1/
A B
1 2
& 1D
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
CLK 8
A B
1 2
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
CLR
9 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403D APRIL 1998 REVISED JANUARY 2001
typical clear, shift, and clear sequences
CLR Serial Inputs A B CLK QA QB QC Outputs QD QE QF QG QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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