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Part: SN74LV164ADR
Category:
Logic
-> Registers
Description: ti SN74LV164A, 8-Bit Parallel-out Serial Shift Registers
Company: Texas Instruments, Inc.
Datasheet: Download SN74LV164ADR datasheet File size : 214 kB
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Datasheet text preview:
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403F APRIL 1998 REVISED JULY 2003
D D D D D
2-V to 5.5-V VCC Operation Max tpd of 10.5 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports
SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
D D
Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN74LV164A . . . RGY PACKAGE (TOP VIEW)
SN54LV164A . . . FK PACKAGE (TOP VIEW)
GND
NC No internal connection
description/ordering information
The 'LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION
TA PACKAGE QFN RGY SOIC D SOP NS 40°C to 85°C SSOP DB TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC FK Reel of 1000 Tube of 50 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74LV164ARGYR SN74LV164AD SN74LV164ADR SN74LV164ANSR SN74LV164ADBR SN74LV164APW SN74LV164APWR SN74LV164APWT SN74LV164ADGVR SNJ54LV164AJ SNJ54LV164AW SNJ54LV164AFK LV164A SNJ54LV164AJ SNJ54LV164AW LV164A TOP-SIDE MARKING LV164A LV164A 74LV164A LV164A
SNJ54LV164AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC CLK CLR
A B QA QB QC QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC QH QG QF QE CLR CLK
1
14 13 QH 12 QG 11 QF 10 QE 9 CLR
B A NC VCC QH QA NC QB NC QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
VCC
A
B QA QB QC QD
2 3 4 5 6 7 8
QG NC QF NC QE
CLK
1
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403F APRIL 1998 REVISED JULY 2003
description/ordering information (continued)
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input.
FUNCTION TABLE INPUTS CLR L H H H CLK X L A X X H L B X X H X QA L QA0 H L OUTPUTS QB . . . QH L QB0 QAn QAn L Q H0 QGn QGn
H X L L QAn QGn QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = the level of QA or QG before the most recent transition of the clock: indicates a 1-bit shift.
logic diagram (positive logic)
CLK 8
A B
1 2
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
CLR
9 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403F APRIL 1998 REVISED JULY 2003
typical clear, shift, and clear sequences
CLR Serial Inputs A B CLK QA QB QC Outputs QD QE QF QG QH
Clear
Clear
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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