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Part: SN74LV164DR
Category:
Logic
-> Registers
Description: ti SN74LV164, 8-Bit Parallel-out Serial Shift Register
Company: Texas Instruments, Inc.
Datasheet: Download SN74LV164DR datasheet File size : 214 kB
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Datasheet text preview:
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B FEBRUARY 1993 REVISED APRIL 1996
D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs
SN54LV164 . . . J OR W PACKAGE SN74LV164 . . . D, DB, OR PW PACKAGE (TOP VIEW)
A B QA QB QC QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC QH QG QF QE CLR CLK
SN54LV164 . . . FK PACKAGE (TOP VIEW)
B A NC VCC QH QA NC QB NC QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
These 8-bit parallel-out serial shift registers are designed for 2.7-V to 5.5-V VCC operation.
QG NC QF NC QE
The 'LV164 feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data as a low at either input inhibits NC No internal connection entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. The SN74LV164 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV164 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LV164 is characterized for operation from 40°C to 85°C.
QD GND NC CLK CLR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
1
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B FEBRUARY 1993 REVISED APRIL 1996
FUNCTION TABLE INPUTS CLR L H H H H CLK X L A X X H L X B X X H X L QA L QA0 H L L OUTPUTS QB . . . QH L QB0 QAn QAn QAn L Q H0 QGn QGn QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state inputs conditions were established QAn, QGn = the level of QA or QG before the most recent transition of the clock: indicates a 1-bit shift
logic symbol
CLR CLK 9 8 SRG8 R C1/
A B
1 2
& 1D
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, DB, J, PW, and W packages.
logic diagram (positive logic)
CLK 8
A B
1 2
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
CLR
9 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B FEBRUARY 1993 REVISED APRIL 1996
typical clear, shift, and clear sequences
CLK Serial Inputs A B CLR QA QB QC Outputs QD QE QF QG QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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