|Category||Semiconductors => Logic => Little Logic|
|Part family||SN74LVC1G125 Single Bus Buffer Gate With 3-State Outputs|
|Title||Bus Oriented Circuits|
|Description||Single Bus Buffer Gate With 3-State Outputs 5-SOT-23 -40 to 125|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74LVC1G125 datasheet
|Cross ref.||Similar parts: SN74LS126AD, SN74LS126ADR2, SN74LS126AM, SN74LS126AMEL, IDT74ALVC125DC, IDT74ALVC125DC8, IDT74ALVC125DCG, IDT74ALVC125PG, IDT74ALVC125PG8, IDT74ALVC126DC|
|Output Drive (IOL/IOH)(Max)(mA)||32/-32|
|ICC @ Nom Voltage(Max)(mA)||0.01|
|F @ Nom Voltage(Max)(Mhz)||150|
|Operating Temperature Range(C)||-40 to 125,-40 to 85|
|tpd @ Nom Voltage(Max)(ns)||9,5.5,4.5,4|
|Approx. Price (US$)||0.07 | 1ku|
|Special Features||Ioff,down translation to Vcc,low power,3-state|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• LVC Characterization Information
This document provides characterization information about low-voltage logic (LVL) that operates from a 3.3-V power supply. It addresses the issues of interfacing to 5-V logic, ac performance, power considerations, input and output characteristics, and sign | Doc
|• Input and Output Characteristics of Digital Integrated Circuits
This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding | Doc
|• How to Select Little Logic (Rev. A)
TI Little Logic devices are logic-gate devices assembled in a small single-, dual-, or triple- gate package. Little Logic devices are widely used in portable equipment, such as mobile phones, MP3 players, and notebook computers. Little Logic devices also a | Doc
|• Understanding Advanced Bus-Interface Products Design Guide | Doc|
|• Selecting the Right Texas Instruments Signal Switch
Texas Instruments offers a wide variety of electronic switches (digital, analog, bilateral, bilateral analog) in a variety of families, including CBT, CBTLV, HC, LV, and LVC. Depending on the application, the right solution may be an analog switch that pas | Doc
|• Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
This application report explores the possibilities for migrating to 3.3-V and 2.5-V power supplies and discusses the implications.Customers are successfully using a wide range of low-voltage, 3.3-V logic devices. These devices are within Texas Instruments | Doc
|• Live Insertion
Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance | Doc
|• Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this, interface terminals of the card must be electrically isolated from the bus system | Doc
|• Use of the CMOS Unbuffered Inverter in Oscillator Circuits
CMOS devices have a high input impedance, high gain, and high bandwidth. These characteristics are similar to ideal amplifier characteristics and, hence, a CMOS buffer or inverter can be used in an oscillator circuit in conjunction with other passive compo | Doc
|• Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to iden | Doc
|• Texas Instruments Little Logic Application Report
Portable and consumer electronic systems? needs present greater challenges today than ever before. Engineers strive to design smaller, faster, lower-cost systems to meet the market demand. Consequently, the semiconductor industry faces a growing need to in | Doc
|• 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
TI?s 56-ball MicroStar Jr.E package, registered under JEDEC MO-225, has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance, improving thermal performance, and minimizing board area usage | Doc
|• Selecting the Right Level Translation Solution (Rev. A)
Supply voltages continue to migrate to lower nodes to support today's low-power, high-performance applications. While some devices are capable of running at lower supply nodes, others might not have this capability. To haveswitching compatibility between t | Doc
|• CMOS Power Consumption and CPD Calculation (Rev. B)
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result, CMOS devices are best known for low power consumpti | Doc
|PP-SALB2-EVM: Smart Amplifier Speaker Characterization Board Evaluation Module|
|TMDXEVM388: DM388 DaVinci Digital Media Processor Evaluation Module|
|DLPLCR4500EVM: DLPÂ® LightCrafterâ„˘ 4500|
|TAS2560EVM: TAS2560 5.6W Class-D Audio Amplifier Evaluation Module|
|TAS5722LEVM: TAS5722L Digital Input Mono Class-D Audio Amplifier Evaluation Module|
|HSPICE Model for SN74LVC1G125 - ZIP (05/15/2007)|
|SN74LVC1G125 PSpice Model - ZIP (06/17/2016)|
Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages 5.5 V Max tpd 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 2000-V Human-Body Model 200-V Machine Model 1000-V Charged-Device Model (C101)
This bus buffer gate is designed for to 5.5-V VCC operation. The is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA NanoStar WCSP (DSBGA) YEA to 85°C NanoFree WCSP (DSBGA) YZA (Pb-free) SOT (SOT 23) DBV to 85°C PACKAGE Reel of 3000 Reel of 3000 Reel of 3000 Reel of 250 Reel of 3000 SOT (SC-70) (SC 70) DCK Reel of 250 ORDERABLE PART NUMBER CM _ _CM_ SN74LVC1G125DCKT CM CM_ C25 C25_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 6.5 V Input voltage range, VI (see Note 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and V to VCC 0.5 V Input clamp current, IIK (VI 50 mA Output clamp current, IOK (VO 50 mA Continuous output current, IO. ±50 mA Continuous current through VCC or GND. ±100 mA Package thermal impedance, JA (see Note 3): DBV package. 206°C/W DCK package. 252°C/W YEA/YZA package. 154°C/W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
MIN VCC Supply voltage Operating Data retention only VCC 1.95 V VCC 2.7 V VCC 3.6 V VCC 5.5 V VCC 1.95 V VCC 2.7 V VCC 3.6 V VCC V 0 VCC 1.65 V VCC 2.3 V IOH High-level output current VCC 3 V VCC 4.5 V VCC 1.65 V VCC 2.3 V IOL Low-level output current VCC 3 V VCC 4.5 V VCC 0.2 V t/v Input transition rise or fall rate VCC 0.3 V VCC 0.5 V VCC 0.35 × VCC 5.5 VCC ns/V mA MAX 5.5 UNIT V
TA Operating free-air temperature 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|SN74LVC1G125DBV Single Bus Buffer Gate With 3-state Outputs|
|SN74LVC1G125DBVR ti SN74LVC1G125, Single Bus Buffer Gate With 3-State Outputs|
|SN74LVC1G125DCK Single Bus Buffer Gate With 3-state Outputs|
|SN74LVC1G125DCKR ti SN74LVC1G125, Single Bus Buffer Gate With 3-State Outputs|
|SN74LVC1G125Q Q1 - Automotive Catalog Single Bus Buffer Gate With 3-State Output|
|SN74LVC1G125YEAR ti SN74LVC1G125, Single Bus Buffer Gate With 3-State Outputs|
|SN74LVC1G126 Single Bus Buffer Gate With 3-state Outputs|
|SN74LVC1G126DBVR ti SN74LVC1G126, Single Bus Buffer Gate With 3-State Outputs|
|SN74LVC1G126DCK Single Bus Buffer Gate With 3-state Outputs|
|SN74LVC1G126DCKR ti SN74LVC1G126, Single Bus Buffer Gate With 3-State Outputs|
|SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-trigger Input|
|SN74LVC1G14 Single Schmitt-trigger Inverter|
|SN74LVC1G14DBVR ti SN74LVC1G14, Single Schmitt-trigger Inverter|
|SN74LVC1G14DCK Single Schmitt-trigger Inverter|
|SN74LVC1G14DCKR ti SN74LVC1G14, Single Schmitt-trigger Inverter|
|SN74LVC1G175 Single D-type Flip-flop With Asynchronous Clear|
|SN74LVC1G17DBVR ti SN74LVC1G17, Single Schmitt-trigger Buffer|
|SN74LVC1G18 One of Two Noninverting Demultiplexer With 3-State Deselected Output|
74F538 : Bipolar->F Family. 1-of-8 Decoder With 3-STATE Outputs. The 74F538 decoder/demultiplexer accepts three Address (A0A2) input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high impedance state.
74HC/HCT390 : CMOS/BiCMOS->HC/HCT Family. Dual Decade Ripple Counter. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family s The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines Product File under Integrated Circuits, IC06 December 1990 Two BCD decade or bi-quinary counters One package can be configured or 100 Two master reset inputs.
74V2G08CTR : Dual 2-Input And Gate. HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) to 5.5V IMPROVED LATCH-UP IMMUNITY The is an advanced.
74V2T126CTR : Dual Bus Buffer (3-State). HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) to 5.5V IMPROVED LATCH-UP IMMUNITY The is an advanced.
AS7512DI : di CMOS Protected Analog Switches.
BU4030B : . The / F and / F are exclusive OR gates. Four circuits are contained on a single chip. An inverter-based buffer is added to the gate output for an enhanced / O voltage characteristic, and the load capacitance has been increased to minimize fluctuation in the propagation time. In addition, these products feature low power consumption and a high noise.
CD54HCT32 : CMOS/BiCMOS->HC/HCT Family. High Speed CMOS Logic Quad 2-input OR GATE.
HCC4040BC1 : Ripple-carry Binary Counter/dividers. MEDIUM-SPEED OPERATION FULLY STATIC OPERATION COMMON RESET BUFFERED INPUTS AND OUTPUTS QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD.
IDT29FCT520A : Multilevel Pipeline Register. Equivalent to AMD's Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage supply extremes Four 8-bit high-speed registers Dual two-level or single four-level push-only stack operation All registers available at multiplexed output Hold, transfer and load instructions Provides temporary.
IDT74FCT16652AT : Bus Oriented Circuits. Fast CMOS 16-bit Bus Transceiver/register. MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1µ A (max.) ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC 5V ±10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP.
KIC7S66FU : = Analog Switch ;; Package = Usv.
N74F399D : Registers. * Discontinued part. Please see the Discontinued Product List. Product Supersedes data of 1990 Apr 08 IC15 Data Handbook 74F398 Quad 2-Port Register with True and Complementary Outputs 74F399 Quad 2-Port Register Select inputs from two data sources Fully positive edge-triggered Both True and Complementary outputs74F398 The 74F398 and 74F399 are the logical.
PI74STX1G86 : Single 2-Input Exclusive OR GATE. High-speed: tPD = 2.6ns typical into @ 5V VCC Broad operating range: VCC 1.65V 5.5V Power down high-impedance inputs/outputs High output drive: at 3V VCC Package: 5-pin space saving SOT23 and SC70 The a 2-input exclusive OR gate that operates over the to 5.5V VCC operating range. Pericoms PI74STX series of products are produced using the Companys advanced.
SN74ALS352D : Multiplexers. ti SN74ALS352, Dual 4-Line to 1-Line Data Selectors/multiplexers.
SN74LV161A : CMOS/BiCMOS->LV/LVQ/LVX Family->Low Voltage. 4-bit Synchronous Binary Counters.
SN74LV32ADB : Quadruple 2-input Positive-OR GATEs. EPICTM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) V at VCC, = 25°C Typical VOHV (Output VOH Undershoot) V at VCC, = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model = 200 pF, = 0) Package Options Include Plastic Small-Outline.