|Category||Logic => Line Driver/Receivers => CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage|
|Title||CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage|
|Description||Octal Buffer/driver With 3-state Outputs|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74LVC244A datasheet|
|Quote||Find where to buy SN74LVC244A|
Operates From 3.6 V Inputs Accept Voltages 5.5 V Max tpd 3.3 V Typical VOLP (Output Ground Bounce) V at VCC = 25°C Typical VOHV (Output VOH Undershoot) V at VCC = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 2000-V Human-Body Model 200-V Machine Model 1000-V Charged-Device Model (C101)
This octal buffer/line driver is operational to 3.6-V VCC, but is designed specifically for to 3.6-V VCC operation. The SN74LVC244A is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
TA PDIP N QFN RGY SOIC to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV VFBGA GQN PACKAGE Tube Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74LVC244ADGVR SN74LVC244AGQNR TOP-SIDE MARKING LVC244A LC244A
VFBGA ZQN (Pb-Free) Tape and reel SN74LVC244AZQNR LC244A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Inputs can be driven from either or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.FUNCTION TABLE (each buffer) INPUTS OE OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 6.5 V Input voltage range, VI (see Note 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and V to VCC 0.5 V Input clamp current, IIK (VI 50 mA Output clamp current, IOK (VO 50 mA Continuous output current, IO. ±50 mA Continuous current through VCC or GND. ±100 mA Package thermal impedance, JA (see Note 3): DB package. 70°C/W (see Note 3): DW package. 58°C/W (see Note 3): DGV package. 92°C/W (see Note 3): GQN/ZQN package. 78°C/W (see Note 3): N package. 69°C/W (see Note 3): NS package. 60°C/W (see Note 3): PW package. 83°C/W (see Note 4): RGY package. 37°C/W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.
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