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Part: SN74LVCZ161284A
Category:
Logic
-> Transceivers
Description:
Company: Texas Instruments, Inc.
Datasheet: Download SN74LVCZ161284A datasheet File size : 233 kB
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Datasheet text preview:
SN74LVCZ161284A 19-BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
SCES358B SEPTEMBER 2001 REVISED SEPTEMBER 2002
D D D D D D D D
Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9A13 Operates From 3 V to 3.6 V 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Ioff and Power-Up 3-State Support Hot Insertion Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 4000-V Human-Body Model (A114-A) 350-V Machine Model (A115-A) 1500-V Charged-Device Model (C101)
DGG PACKAGE (TOP VIEW)
description/ordering information
The SN74LVCZ161284A is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
HD A9 A10 A11 A12 A13 VCC A1 A2 GND A3 A4 A5 A6 GND A7 A8 VCC PERI LOGIC IN A14 A15 A16 A17 HOST LOGIC OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DIR Y9 Y10 Y11 Y12 Y13 VCC CABLE B1 B2 GND B3 B4 B5 B6 GND B7 B8 VCC CABLE PERI LOGIC OUT C14 C15 C16 C17 HOST LOGIC IN
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
0°C to 70°C TSSOP DGG Tape and reel SN74LVCZ161284AGR LVCZ161284A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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· DALLAS, TEXAS 75265
1
SN74LVCZ161284A 19-BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
SCES358B SEPTEMBER 2001 REVISED SEPTEMBER 2002
description/ordering information (continued)
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low. The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant. The Power-On Reset (POR) ensures that the Y outputs (Y9Y13) stay in the high state after power on until an associated input (A9A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power on.
FUNCTION TABLE INPUTS DIR L L H H HD L H L H OUTPUT Open drain Totem pole Totem pole Open drain Totem pole Totem pole MODE A9A13 to Y9Y13 and PERI LOGIC IN to PERI LOGIC OUT B1B8 to A1A8 and C14C17 to A14A17 B1B8 to A1A8, A9A13 to Y9Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14C17 to A14A17 A1A8 to B1B8, A9A13 to Y9Y13, and PERI LOGIC IN to PERI LOGIC OUT C14C17 to A14A17 A1A8 to B1B8, A9A13 to Y9Y13, C14C17 to A14A17, and PERI LOGIC IN to PERI LOGIC OUT
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVCZ161284A 19-BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
SCES358B SEPTEMBER 2001 REVISED SEPTEMBER 2002
logic diagram
VCC CABLE DIR HD 42 48 1 See Note A See Note A See Note B
A1A8
B1B8
A9A13 Y9Y13 See Note C
PERI LOGIC IN
19
30
PERI LOGIC OUT
A14A17 24 25
C14C17
HOST LOGIC OUT
HOST LOGIC IN
NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. C. Active input detection circuit forces Y9Y13 to the high state after power on, until one of the A9A13 pins goes high (see below).
D A9 A10 A11 A12 A13 Timer C R Power-On Reset
Q
OUT
Active Input Detection Circuit
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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