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Details, datasheet, quote on part number:SNJ54AS74AFK
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| Part: | SNJ54AS74AFK |
| Category: | Logic => Flip-Flops => D-Type Flip-Flops |
| Description: | ti SN54AS74A, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SNJ54AS74AFK datasheet File size : 117 kB |
| Request For quote: | Find where to buy SNJ54AS74AFK
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Datasheet text preview:
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDAS143C APRIL 1982 REVISED AUGUST 1995
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Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF) (MHz) 50 134 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 26
SN54ALS74A, SN54AS74A . . . J PACKAGE SN74ALS74A, SN74AS74A . . . D OR N PACKAGE (TOP VIEW)
TYPE ALS74A AS74A
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VC C 2CLR 2D 2CLK 2PRE 2Q 2Q
description
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS PRE L H L H H CLR H L L H H CLK X X X D X X X H L
SN54ALS74A, SN54AS74A . . . FK PACKAGE (TOP VIEW)
1CLK NC 1PRE NC 1Q
1D 1CLR NC VCC 2CLR
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2D NC 2CLK NC 2PRE
NC No internal connection
OUTPUTS Q H L H H L Q L H H L H
H H L X Q0 Q0 The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1Q GND NC 2Q 2Q
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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDAS143C APRIL 1982 REVISED AUGUST 1995
logic symbol
1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 3 2 1 10 11 12 8 13 2Q S C1 1D R 9 6 1Q 5 1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
PRE
CLR
Q
Q CLK
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SDAS143C APRIL 1982 REVISED AUGUST 1995
recommended operating conditions
SN54ALS74A MIN VCC VIH VIL IOH IOL fclock tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency PRE or CLR low Pulse duration CLK high CLK low tsu th TA Setup time before CLK time before CLK Hold time after CLK Operating free-air temperature Data PRE or CLR inactive Data 0 15 17.5 17.5 16 10 2 55 125 4.5 2 0.7 0.4 4 25 0 15 14.5 14.5 15 10 0 0 70 ns ns °C ns NOM 5 MAX 5.5 SN74ALS74A MIN 4.5 2 0.8 0.4 8 34 NOM 5 MAX 5.5 UNIT V V V mA mA MHz
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL CLK or D PRE or CLR CLK or D PRE or CLR CLK or D PRE or CLR TEST CONDITIONS CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 V, VCC = 4 5 V 4.5 V, VCC = 4 5 V 4.5 V, II = 18 mA IOH = 2 mA IOL = 4 mA IOL = 8 mA VI = 7 V VI = 2 7 V 2.7 VI = 0 4 V 0.4 SN54ALS74A MIN TYP MAX 1.5 VCC 2 0.25 0.4 0.1 0.2 20 40 0.2 0.4 VCC 2 0.25 0.35 0.4 0.5 0.1 0.2 20 40 0.2 0.4 SN74ALS74A MIN TYP MAX 1.5 UNIT V V V mA µA mA
IO VCC = 5.5 V, VO = 2.25 V 20 112 30 112 mA ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA All typical values are at VCC = 5 V, TA = 25°C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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