|Category||Semiconductors => Audio => Mid-Power Audio Amplifiers (10-50W) => Digital I2S Input Class-D|
|Part family||TAS5342 100-W Stereo Digital Amplifier Power Stage|
|Description||100-W Stereo Digital Amplifier Power Stage 44-HTSSOP 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TAS5342 datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
The is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4- bridge-tied load (BTL) 100 W per channel with low harmonic distortion, low integrated noise, and low idle current. The TAS5342 has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of PWM signal (PWM activity detector). A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs.
Total Power Output (Bridge Tied Load) at 10% THD+N Into at 10% THD+N Into at 10% THD+N Into 8 Total Power Output (Single Ended) at 10% THD+N Into at 10% THD+N Into 4 Total Power Output (Parallel Mode) at 10% THD+N Into at 10% THD+N Into >110 dB SNR (A-Weighted With TAS5518 Modulator) <0.1% THD+N W, 1 kHz) Supports PWM Frame Rates of 192 kHz to 432 kHz Resistor-Programmable Current Limit Integrated Self-Protection Circuitry, Including: Under Voltage Protection Overtemperature Warning and Error Overload Protection Short-Circuit Protection PWM Activity Detector Standalone Protection Recovery Power-On Reset (POR) to Eliminate System Power-Supply Sequencing High-Efficiency Power Stage (>90%) With 80-m Output MOSFETs Thermally Enhanced Package 44-Pin HTSSOP (DDV) Error Reporting, 3.3-V and 5.0-V Compliant EMI Compliant When Used With Recommended System DesignAPPLICATIONS
Mini/Micro Audio System DVD Receiver Home Theater
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPad are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5342 is available in a thermally enhanced package 44-pin HTSSOP PowerPadTM package (DDV) This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling to the heatsink.GVDD_B OTW NC SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M2 M1 PWM_C RESET_CD PWM_D NC VDD GVDD_C
GVDD_A BST_A NC PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D NC BST_D GVDD_DSubmit Documentation Feedback Product Folder Link(s): TAS5342
Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
Description All protection systems enabled Latching shudown on, PWM activity detector and OLP disabled All protection systems enabled All protection systems enabled All protection systems enabled (3) Latching shudown on, PWM activity detector and OLP disabled (3) Reserved
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode. PPSC detection system disabled.
PARAMETER RJC (°C/W)--2 BTL 4 SE channels RJC (°C/W)--1 BTL 2 SE channel(s) RJC (°C/W)--1 SE channel Power Pad area (1) (2)
JC is junction-to-case, CH is case-to-heatsink. RCH is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K between the pad area and the heat sink. The RCH with this condition is 0.6°C/W for the DDV package.
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