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Part: TLC1550INW
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: ti TLC1550, 10-Bit, 164 KSPS ADC Parallel Out, Direct I/f to DSP/uProcessor, 10 Ch.
Company: Texas Instruments, Inc.
Datasheet: Download TLC1550INW datasheet File size : 619 kB
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Datasheet text preview:
TLC1550I, TLC1550M, TLC1551I 10 BIT ANALOG TO DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
SLAS043G - MAY 1991 - REVISED NOVEMBER 2003
D Power Dissipation . . . 40 mW Max D Advanced LinEPIC Single-Poly Process D D D D D
Provides Close Capacitor Matching for Better Accuracy Fast Parallel Processing for DSP and µP Interface Either External or Internal Clock Can Be Used Conversion Time . . . 6 µs Total Unadjusted Error . . . ±1 LSB Max CMOS Technology
J OR DW PACKAGE (TOP VIEW)
description
The TLC1550x and TLC1551 are data acquisition analog-to-digital converters (ADCs) using a 10-bit, switched-capacitor, successive-approximation network. A high-speed, 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). Separate power terminals for the analog and digital portions minimize noise pickup in the supply leads. Additionally, the digital power is divided into two parts to separate the lower current logic from the higher current bus drivers. An external clock can be applied to CLKIN to override the internal system clock if desired. The TLC1550I and TLC1551I are characterized for operation from - 40°C to 85°C. The TLC1550M is characterized over the full military range of - 55°C to 125°C.
REF+ REF - ANLG GND AIN ANLG VDD DGTL GND1 DGTL GND2 DGTL VDD1 DGTL VDD2 EOC D0 D1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
RD WR CLKIN CS D9 D8 D7 D6 D5 D4 D3 D2
Refer to the mechanical data for the JW package.
AIN ANLG V DD DGTL GND1 NC DGTL GND2 DGTL VDD1 DGTL VDD2
ANLG GND REF- REF+ NC RD WR CLKIN
5 6 7 8 9 10 4 NC - No internal connection PACKAGE CERAMIC DIP (J) -- TLC1550MJ --
FK OR FN PACKAGE (TOP VIEW)
3 2 1 28 27 26
25 24 23 22 21
20 11 19 12 13 14 15 16 17 18
CS D9 D8 NC D7 D6 D5
AVAILABLE OPTIONS TA - 40°C to 85°C - 55°C to 125°C CERAMIC CHIP CARRIER (FK) -- TLC1550MFK PLASTIC CHIP CARRIER (FN) TLC1550IFN TLC1551IFN SOIC (DW) TLC1550IDW TLC1551IDW --
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinEPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
EOC D0 D1 NC D2 D3 D4
Copyright 2003, Texas Instruments Incorporated
1
SLAS043G - MAY 1991 - REVISED NOVEMBER 2003
TLC1550I, TLC1550M, TLC1551I 10 BIT ANALOG TO DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
functional block diagram
EOC
CS WR RD
Control Logic
SuccessiveApproximation Register
10 D0 - D9
10 DGTL VDD1 100 k NOM Frequency Divided by 2 Internal Clock 10-Bit Capacitor DAC and S/H Clock Detector
Comp
CLKIN REF + REF - AIN
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE 1 k TYP AIN Ci = 60 pF TYP (equivalent input capacitance) AIN 5 M TYP INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I 10 BIT ANALOG TO DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
SLAS043G - MAY 1991 - REVISED NOVEMBER 2003
Terminal Functions
NAME AIN ANLG VDD CLKIN TERMINAL NO. 4 5 6 26 NO. 3 4 5 22 DESCRIPTION Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF-. Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output. Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3. Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high or left unconnected. Chip-select. CS must be low for RD or WR to be recognized by the A/D converter. Data bus output. D0 is bit 1 (LSB). Data bus output. D1 is bit 2. Data bus output. D2 is bit 3. Data bus output. D3 is bit 4. Data bus output. D4 is bit 5. Data bus output. D5 is bit 6. Data bus output. D6 is bit 7. Data bus output. D7 is bit 8. Data bus output. D8 is bit 9. Data bus output. D9 is bit 10 (MSB). Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connection Digital ground 2. The ground for power supply DGTL VDD2 Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 is designated VDD1. Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltage applied to DGTL VDD2 is designated VDD2. End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred to the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled. Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD resets EOC to a high within the td(EOC) specifications. Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts to 1111111111. Analog input voltages between REF + and REF - convert to the appropriate result in a ratiometric manner. Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF - converts to 0000000000. Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds the analog input until conversion is completed. Before and after the conversion period, which is given by t conv, the ADC remains in the sampling mode.
ANLG GND
CS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DGTL GND1 DGTL GND2 DGTL VDD1 DGTL VDD2 EOC RD
25 13 14 16 17 18 19 20 21 23 24 7 9 10 11 12 28
21 11 12 13 14 15 16 17 18 19 20 6 7 8 9 10 24
REF+
2
1
REF - WR
3 27
2 23
Terminal numbers for FK and FN packages. Terminal numbers for J, DW, and NW packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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