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Part: TLC2578
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
-> 10-14 bit
-> 12 bit
Description:
Company: Texas Instruments, Inc.
Datasheet: Download TLC2578 datasheet File size : 619 kB
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Datasheet text preview:
TLC3574, TLC3578, TLC2574, TLC2578 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH ±10-V INPUTS
SLAS262B OCTOBER 2000 REVISED AUGUST 2001
D D D
D D D D D D D D D D D D D
14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578 Maximum Throughput 200-KSPS Multiple Analog Inputs: 8 Single-Ended Channels for TLC3578/2578 4 Single-Ended Channels for TLC3574/2574 Analog Input Range: ±10 V Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz Built-In Conversion Clock and 8x FIFO Single 5-V Analog Supply; 3-/5-V Digital Supply Low-Power 5.8 mA in Normal Operation 20 µA in Power Down Programmable Autochannel Sweep and Repeat Hardware-Controlled, Programmable Sampling Period Hardware Default Configuration INL: TLC3574/78: ±1 LSB; TLC2574/78: ±0.5 LSB DNL: TLC3574/78: ±0.5 LSB; TLC2574/78: ±0.5 LSB SINAD: TLC3574/78: 79 dB; TLC2574/78: 72 dB THD: TLC3574/78: 82 dB; TLC2574/78: 82 dB
TLC3578, TLC2578 DW OR PW PACKAGE (TOP VIEW)
SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
CSTART AVDD AGND COMP REFM REFP AGND AVDD A7 A6 A5 A4
TLC3574, TLC2574 DW, N, OR PW PACKAGE (TOP VIEW)
SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
CSTART AVDD AGND COMP REFM REFP AGND AVDD A3 A2
description
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SLAS262B OCTOBER 2000 REVISED AUGUST 2001
TLC3574, TLC3578, TLC2574, TLC2578 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH ±10-V INPUTS
description (continued)
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.
AVAILABLE OPTIONS PACKAGED DEVICES TA 40°C to 85°C to 85°C 20-TSSOP (PW) TLC2574IPW TLC3574IPW 20-SOIC (DW) TLC2574IDW TLC3574IDW 20-PDIP (N) TLC2574IN TLC3574IN 24-SOIC (DW) TLC2578IDW TLC3578IDW 24-TSSOP (PW) TLC2578IPW TLC3578IPW
functional block diagram
DVDD REFP COMP REFM AVDD
X8 X4 A0 A0 A1 A1 A2 A2 A3 A3 X A4 X A5 X A6 X A7
Analog MUX Signal Scaling OSC
SAR ADC
FIFO X8
SDO Command Decode Conversion Clock
CFR SDI CMR (4 MSBs) SCLK CS FS 4-Bit Counter CSTART
Control Logic
EOC/INT
TLC3578, TLC2578 TLC3574, TLC2574
DGND AGND
NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated in by CS falling edge if CS initiates the conversion operation cycle, or gated in by the rising edge of FS if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC3574, TLC3578, TLC2574, TLC2578 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH ±10-V INPUTS
SLAS262B OCTOBER 2000 REVISED AUGUST 2001
equivalent input circuit
REFP Bipolar Signal Scaling MUX 3.94 k 9.9 k Ain 6.6 k Equivalent Digital Input Circuit Ron C(sample)= 30 pF 1.5 k Digital Input VDD
REFM Diode Turn on Voltage: 35 V Equivalent Analog Input Circuit
Terminal Functions
TERMINAL NO. NAME A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 TLC3574 TLC2574 9 10 11 12 TLC3578 TLC2578 9 10 11 12 13 14 15 16 18, 22 17, 23 21 8 I Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The driving source impedance should be less than or equal to 25 for normal sampling. For larger source impedance, use the external hardware conversion start signal CSTART (the low time of CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling time. I/O DESCRIPTION
AGND AVDD COMP CS
14, 18 13, 19 17 8
I I I I
Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with respect to AGND. Analog supply voltage Internal compensation pin. Install compensation capacitors 0.1 µF between this pin and AGND. Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is disabled to clock data, but works as conversion clock source if programmed. The falling edge of CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from high-impedance state. If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave select (SS) to provide an SPI interface. If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip select to allow host to access the individual converter.
CSTART
20
24
I
External sampling trigger signal, which initiates the sampling from a selected analog input channel when the device works in extended sampling mode (asynchronous sampling). A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. The low time of the CSTART signal controls the sampling period. CSTART signal must stay low long enough for proper sampling. CSTART must stay high long enough after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued before the rising edge of the eleventh SCLK. Tie this pin to DVDD if not used. Digital ground return for the internal circuitry Digital supply voltage
DGND DVDD
6 7
6 7
I I
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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