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Part: TLV0838IN
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: ti TLV0838, 8-Bit 37.9 KSPS ADC Serial Out, Ratiometric op or VCC Ref, Ttl/mos Input & Output Compatible, 8 Ch.
Company: Texas Instruments, Inc.
Datasheet: Download TLV0838IN datasheet File size : 402 kB
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Datasheet text preview:
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147B SEPTEMBER 1996 REVISED OCTOBER 2000
D D D D D D
8-Bit Resolution 2.7-V to 3.6-V VCC Easy Microprocessor Interface or Stand-Alone Operation Operates Ratiometrically or With VCC Reference 4- or 8-Channel Multiplexer Options With Address Logic Input Range 0 V to VCC With VCC Reference
D D D D D
Remote Operation With Serial Data Link Inputs and Outputs Are Compatible With TTL and MOS Conversion Time of 32 µs at f(CLK) = 250 kHz Functionally Equivalent to the ADC0834 and ADC0838 at 3-V Supply Without the Internal Zener Regulator Network Total Unadjusted Error . . . ±1 LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters, each with an input-configurable multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is readily available from the factory. The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software-configured for single-ended or differential inputs as well as pseudodifferential input assignments. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution. The TLV0834C and TLV0838C are characterized for operation from 0°C to 70°C. The TLV0834I and TLV0838I are characterized for operation from 40°C to 85°C.
TLV0834 . . . D OR N PACKAGE (TOP VIEW) TLV0834 . . . PW PACKAGE (TOP VIEW) TLV0838 . . . PW, DW, OR N PACKAGE (TOP VIEW)
NC CS CH0 CH1 CH2 CH3 DGTL GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC DI CLK SARS DO REF ANLG GND
NC CS CH0 CH1 CH2 CH3 DGTL GND NC
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC DI CLK SARS DO REF ANLG GND NC
NC No internal connection
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGTL GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC CS DI CLK SARS DO SE REF ANLG GND
AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C 40°C to 85°C SMALL OUTLINE (D) TLV0834CD TLV0834ID SMALL OUTLINE (DW) TLV0838CDW TLV0838IDW PLASTIC DIP (N) TLV0834CN TLV0834IN TLV0838CN TLV0838IN TSSOP (PW) TLV0834CPW TLV0834IPW TLV0838CPW TLV0838IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SLAS147B SEPTEMBER 1996 REVISED OCTOBER 2000
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
2
functional block diagram
CLK CS DI (see Note A) D CLK
SELECT0 SELECT1 ODD\ EVEN SGL\ DIF START
Start Flip-Flop CLK R 5-Bit Shift Register S R
CS
SARS
TLC0838 Only SE
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To Internal Circuits
TLC0834
TLC0838
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
CLK
Analog MUX
Time Delay
S
R
EN
· DALLAS, TEXAS 75265
CS
Comparator EN REF Ladder and Decoder
CS R SAR Logic and Latch
CS CS R CLK Bits 07 Bit 1 MSB First LSB First 9-Bit Shift Register EOC CS R CLK DO D
Bits 07
One Shot
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147B SEPTEMBER 1996 REVISED OCTOBER 2000
functional description
The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative () polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. The common input on the TLV0838 can be used for a pseudodifferential input. In this mode, the voltage on the common input is considered to be the negative differential input for all channel inputs. This voltage can be any reference potential common to all channel inputs. Each channel input can then be selected as the positive differential input. This feature is useful when all analog circuits are biased to a potential other than ground. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is disabled for the duration of the conversion. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low. The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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