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Part: TLV5590ED
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: ti TLV5590, 2-Bit ADC For FLEX(TM) Pager Chipset
Company: Texas Instruments, Inc.
Datasheet: Download TLV5590ED datasheet File size : 3276 kB
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Datasheet text preview:
TLV5590 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS134B NOVEMBER 1995 REVISED NOVEMBER 1996
D D D D D
Supports FLEXt Protocol Pagers With The TLV5591 FLEX Decoder 3-Pole Butterworth Low-Pass Selectable Dual-Bandwidth Audio Filter BW 1 = 1 kHz ±5% ( 3 dB) BW 2 = 2 kHz ±5% ( 3 dB) Both Peak and Valley Detectors Available 2-Bit Analog-to-Digital Converter Operating Temperature Range . . . 25°C to 85°C
D
D D D
Four Modes of Operation: Fast Acquisition Slow Acquisition Hold Acquisition Standby 2.7-V to 3.3-V Single Power Supply Operation
applications
FLEX Protocol Numeric and Alphanumeric Pagers One-Way or Two-Way
D PACKAGE (TOP VIEW)
description
The TLV5590 analog-to-digital converter is a system level solution to interface a 4-level DVDD 1 14 CLK baseband audio signal to a digital decoder. The AVDD 2 13 TEST TLV5590 is a direct interface to the TLV5591BVF SIG 3 12 TRACKINH FLEX decoder. Designed primarily for pager DC OFFSET 4 11 EXTS0 applications, the TLV5590 incorporates signal MID 5 10 EXTS1 conditioning, both peak and valley detection along GND 6 9 CON2 with analog-to-digital conversion. A selectable BW 7 8 CON1 third-order Butterworth filter with cutoff frequencies of 1 kHz and 2 kHz is included. The peak and valley detectors are implemented with a unique design that does not require external capacitors. Two 8-bit digital-to-analog converters (DACs) are used in a feedback loop to automatically adjust to the peak and valley levels. The DAC outputs are used to set Vref+ and Vref for the 2-bit analog-to-digital converter (ADC). Modes of operation include fast track, slow track, hold, and standby. The standby mode maximizes battery life. The TLV5590 operates on a single supply down to 2.7 V.
AVAILABLE OPTIONS PACKAGE TA 25°C to 85°C SMALL OUTLINE (D) TLV5590ED
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FLEX is a trademark of Motorola, Incorporated. TLV5591BVF Data Manual Literature Number SLWS048
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TLV5590 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS134B NOVEMBER 1995 REVISED NOVEMBER 1996
functional block diagram
MID AVDD 2 5 Peak Detector
+ _
Decay Counter
Up/ Down 4 DC OFFSET fs = 1 kHz Gain = 12 dB nom. 3rd-Order Butterworth 3 SIG FILOUT fs = 2 kHz Gain = 12 dB nom. 3rd-Order Butterworth
CTR
8-Bit DAC
REF + 11 2-Bit ADC Valley Detector Decay Counter 10 EXTS0 EXTS1
REF
CON1 CON2 BW
8 9 7 Mode Control and Enable
Up/ Down
CTR
8-Bit DAC
TRACKINH CLK
12 14
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV5590 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS134B NOVEMBER 1995 REVISED NOVEMBER 1996
Terminal Functions
TERMINAL NAME AVDD BW CON1 CON2 CLK DC OFFSET DVDD EXTS0 EXTS1 GND SIG MID TEST TRACKINH NO. 2 7 8 9 14 4 1 11 10 6 3 5 13 12 I O I I I I I I I I I O O Analog supply voltage Digital bandwidth select. A high level on BW selects the 2-kHz filter cutoff and a low level selects the 1-kHz filter cutoff. Digital control 1 input. In conjunction with CON2, CON1 selects the fast acquisition mode, slow acquisition mode, hold or standby. Digital control 2 input. In conjunction with CON1, CON2 selects the fast acquisition mode, slow acquisition mode, hold or standby. Digital clock input. CLK input is a 50% duty cycle TTL-level clock input with nominal frequency of 38.4 kHz. The CLK input is edge sensitive in all non-test modes. For all test modes, the CLK input is level sensitive. Analog dc offset correction input. The dc component of the audio signal should be applied to DC OFFSET. Digital supply voltage Digital output 0 of the ADC. Data bit 0 is the LSB. Digital output 1 of the ADC. Data bit 1 is the MSB. Return terminal for the IC current. Analog audio signal input. An appropriate RC low-pass filter (antialiasing filter) should be connected to SIG. Analog midpoint output. MID is a buffered output of AVDD/2. Digital test input enable. TEST should be connected to ground in normal operation. Digital track inhibit logic input. A high level on TRACKINH disables the peak and valley detector counters, and a low level enables the peak and valley detector counters. The counters continue to decay at the decay rate while TRACKINH is a low level. I/O DESCRIPTION
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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