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Part: TLV5592D
Category:
Communication
-> Telephony
-> Pager
Description: 2-bit Analog-to-digital Converter For Flex Pager Chipset
Company: Texas Instruments, Inc.
Datasheet: Download TLV5592D datasheet File size : 3276 kB
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Datasheet text preview:
TLV5592 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS145A JUNE1996 REVISED DECEMBER 1997
D D D D D
Supports FLEXt Protocol Messaging Systems With The TLV559X FLEX Decoder 3-Pole Butterworth Low-Pass Selectable Dual-Bandwidth Audio Filter BW 1 = 1 kHz ±5% ( 3 dB) BW 2 = 2 kHz ±5% ( 3 dB) Both Peak and Valley Detectors Available 2-Bit Analog-to-Digital Converter Operating Temperature Range 20°C to 65°C
D
D D D
Four Modes of Operation: Fast Track Slow Track Hold Standby 1.8-V to 2.5-V Single Power Supply Operation
applications
FLEX Protocol Numeric and Alphanumeric Messaging Systems One-Way or Two-Way
description
The Texas Instruments (TITM) TLV5592 analog-todigital converter (ADC) is a system level solution to interface a 4-level baseband audio signal to a digital decoder. The TLV5592 is a direct interface to the TLV559X FLEX decoder. Designed primarily for messaging applications, the TLV5592 incorporates signal conditioning, both peak and valley detection along with analog-to-digital conversion. A selectable third-order Butterworth filter with cutoff frequencies of 1 kHz and 2 kHz is included. The peak and valley detectors are implemented with a unique design that does not require external capacitors. Two 8-bit digital-to-analog converters (DACs) are used in a feedback loop to automatically adjust to the peak and valley levels. The DAC outputs are used to set Vref+ and Vref for the 2-bit ADC. Modes of operation include fast track, slow track, hold, and standby. The standby mode maximizes battery life. The TLV5592 operates on a single power supply from 1.8 V to 2.5 V.
D PACKAGE (TOP VIEW)
DVDD AVDD SIG DC OFFSET MID GND BW
1 2 3 4 5 6 7
14 13 12 11 10 9 8
CLK TEST TRACKINH EXTS0 EXTS1 CON2 CON1
AVAILABLE OPTIONS PACKAGE TA 25°C to 65°C SMALL OUTLINE (D) TLV5592ED
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FLEX is a trademark of Motorola Inc. TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TLV5592 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS145A JUNE1996 REVISED DECEMBER 1997
functional block diagram
MID AVDD 2 5 Peak Detector
+ _
Decay Counter
Up/ Down 4 DC OFFSET fs = 1 kHz Gain = 6 dB nominal 3rd-Order Butterworth 3 SIG FILOUT fs = 2 kHz Gain = 6 dB nominal 3rd-Order Butterworth
CTR
8-Bit DAC
REF + 11 2-Bit ADC Valley Detector Decay Counter 10 EXTS0 EXTS1
REF
CON1 CON2 BW
8 9 7 Mode Control and Enable
Up/ Down
CTR
8-Bit DAC
TRACKINH CLK
12 14
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV5592 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEXt PAGER CHIPSET
SLAS145A JUNE1996 REVISED DECEMBER 1997
Terminal Functions
TERMINAL NAME AVDD BW CON1 CON2 CLK NO. 2 7 8 9 14 I I I I I Analog supply voltage Digital bandwidth select. A high level on BW selects the 2-kHz filter cutoff and a low level selects the 1-kHz filter cutoff. Digital control 1 input. In conjunction with CON2, CON1 selects fast track, slow track, hold, or standby mode. Digital control 2 input. In conjunction with CON1, CON2 selects fast track, slow track, hold, or standby mode. Digital clock input. CLK input is a 50% duty cycle transistor-transistor logic (TTL)-level clock input with nominal frequency of 38.4 kHz. The CLK input is edge sensitive in all non-test modes. For all test modes, the CLK input is level sensitive. Analog dc offset correction input. The dc component of the audio signal should be applied to DC OFFSET. Digital supply voltage Digital output 0 of the ADC. Data bit 0 is the least significant bit (LSB). Digital output 1 of the ADC. Data bit 1 is the most significant bit (MSB). Return terminal for the IC current O I I I Analog midpoint output. MID is a buffered output of AVDD/2. Analog audio signal input. An appropriate resistance capacitance (RC) low-pass filter (antialiasing filter) should be connected to SIG. Digital test input enable. TEST should be connected to ground in normal operation. Digital track inhibit logic input. A high level on TRACKINH disables the peak and valley detector counters; a low level enables the peak and valley detector counters. The counters continue to decay at the decay rate while TRACKINH is a low level. I/O DESCRIPTION
DC OFFSET DVDD EXTS0 EXTS1 GND MID SIG TEST TRACKINH
4 1 11 10 6 5 3 13 12
I I O O
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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