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Part: TLV5604IPWR
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description: ti TLV5604, 10-Bit, 3 us Quad DAC, Serial Input, Simultaneous Update, Programmable Settling Time, Powerdown
Company: Texas Instruments, Inc.
Datasheet: Download TLV5604IPWR datasheet File size : 3276 kB
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Datasheet text preview:
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176B DECEMBER 1997 REVISED JULY 2002
D D D D D D D D D
Four 10-Bit D/A Converters Programmable Settling Time of 3 µs or 9 µs Typ TMS320, (Q)SPI, and Microwire Compatible Serial Interface Internal Power-On Reset Low Power Consumption: 5.5 mW, Slow Mode 5-V Supply 3.3 mW, Slow Mode 3-V Supply Reference Input Buffers Voltage Output Range . . . 2 × the Reference Input Voltage Monotonic Over Temperature Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)
D D D D D D D D D
Hardware Power Down (10 nA) Software Power Down (10 nA) Simultaneous Update
applications
Battery Powered Test Instruments Digital Offset and Gain Adjustment Industrial Process Controls Machine and Motion Control Devices Communications Arbitrary Waveform Generation
D OR PW PACKAGE (TOP VIEW)
description
The TLV5604 is a quadruple 10-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5604 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value.
DVDD PD LDAC DIN SCLK CS FS DGND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
AVDD REFINAB OUTA OUTB OUTC OUTD REFINCD AGND
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND), and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be tied together. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D. The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176B DECEMBER 1997 REVISED JULY 2002
AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C 40°C to 85°C SOIC (D) TLV5604CD TLV5604ID TSSOP (PW) TLV5604CPW TLV5604IPW
functional block diagram
AVDD REFINAB 15 DAC A Power-On Reset + _ x2 14 16 DVDD 1
OUTA
10 14 14-Bit Data and Control Register
DIN
4
Serial Input Register 2
10-Bit DAC Latch
10
2
7 FS 5 SCLK CS 6 DAC Select/ Control Logic
2-Bit Control Data Latch
2 Power Down/ Speed Control
DAC B
13
OUTB
DAC C
12
OUTC
REFINCD
DAC D 3 9 AGND 8 DGND LDAC PD 2
11
OUTD
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176B DECEMBER 1997 REVISED JULY 2002
Terminal Functions
TERMINAL NAME AGND AVDD CS DGND DIN DVDD FS PD LDAC REFINAB REFINCD SCLK OUTA OUTB OUTC OUTD NO. 9 16 6 8 4 1 7 2 3 15 10 5 14 13 12 11 I I I I I I O O O O I I I/O Analog ground Analog supply Chip select. This terminal is active low. Digital ground Serial data input Digital supply Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5604. Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages. This terminal is active low. Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is low. Voltage reference input for DACs A and B. Voltage reference input for DACs C and D. Serial Clock input DAC A output DAC B output DAC C output DAC D output DESCRIPTION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 V to 2.8 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Operating free-air temperature range, TA: TLV5604C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5604I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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