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Part: TLV5606IDR
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description: ti TLV5606, 10-Bit, 3 or 9 us DAC, Serial Input, Pgrmable Settling Time/pwr Consumption, Ultra Low Power
Company: Texas Instruments, Inc.
Datasheet: Download TLV5606IDR datasheet File size : 3276 kB
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Datasheet text preview:
TLV5606 2.7-V TO 5.5-V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS259A DECEMBER 1999 REVISED NOVEMBER 2002
features
D D D D D D
10-Bit Voltage Output DAC Programmable Settling Time vs Power Consumption 3 µs in Fast Mode 9 µs in Slow Mode Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V Differential Nonlinearity . . . <0.2 LSB Typ Compatible With TMS320 and SPI Serial Ports Power-Down Mode (10 nA)
D D D D D D D D D
Buffered High-Impedance Reference Input Voltage Output Range . . . 2 Times the Reference Input Voltage Monotonic Over Temperature Available in MSOP Package
applications
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
D OR DGK PACKAGE (TOP VIEW)
description
The TLV5606 is a 10-bit voltage output digital-toanalog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5606 is programmed with a 16-bit serial string containing 4 control and 10 data bits. Developed for a wide range of supply voltages, the TLV5606 can operate from 2.7 V to 5.5 V.
DIN SCLK CS FS
1 2 3 4
8 7 6 5
VDD OUT REFIN AGND
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0°C to 70°C. The TLV5606I is characterized for operation from 40°C to 85°C.
AVAILABLE OPTIONS TA 0°C to 70°C 40°C to 85°C PACKAGE SMALL OUTLINE (D) TLV5606CD TLV5606ID MSOP (DGK) TLV5606CDGK
TLV5606IDGK Available in tape and reel as the TLV5606CDR, TLV5606IDR, TLV5606CDGKR, and the TLV5606IDGKR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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1
TLV5606 2.7-V TO 5.5-V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
functional block diagram
_ 6 REFIN +
DIN
1
Serial Input Register
12
10 10-Bit Data Latch 10 x2 7 OUT
SCLK CS FS
2 3 4 16 Cycle Timer Update
Power-On Reset
2 Speed/Power-Down Logic
Terminal Functions
TERMINAL NAME AGND CS DIN FS OUT REFIN SCLK VDD NO. 5 3 1 4 7 6 2 8 I I I O I I I/O Analog ground Chip select. Digital input used to enable and disable inputs, active low. Serial digital data input Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. DAC analog output Reference analog input voltage Serial digital clock input Positive power supply DESCRIPTION
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV5606 2.7-V TO 5.5-V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5606C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5606I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage VDD voltage, High-level digital input voltage, VIH digital input voltage Low-level digital input voltage, VIL digital input voltage Reference voltage, Vref to REFIN terminal Reference voltage, Vref to REFIN terminal Load resistance, RL Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA free air temperature TLV5606C TLV5606I 0 40 VDD = 5 V VDD = 3 V DVDD = 2.7 V DVDD = 5.5 V DVDD = 2.7 V DVDD = 5.5 V VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) AGND AGND 2 2.048 1.024 10 100 20 70 85 4.5 2.7 2 2.4 0.6 1 VDD 1.5 VDD 1.5 NOM 5 3 MAX 5.5 3.3 UNIT V V V V V V V V k pF MHz °C °C
NOTE 1: Due to the x2 output buffer, a reference input voltage VDD/2 causes clipping of the transfer function.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS VDD = 5 V, VREF = 2.048 V, No load, All inputs = AGND or VDD, DAC latch = 0x800 VDD = 3 V, VREF = 1.024 V No load, All inputs = AGND or VDD, DAC latch = 0x800 Fast Slow Fast Slow MIN TYP 0.9 0.4 0.7 0.3 10 See Note 2 See Note 3 80 80 2 MAX 1.35 0.6 1.1 0.45 UNIT mA mA mA mA nA dB V
IDD
Power supply current supply current
Power down supply current (see Figure 12) PSRR Power supply rejection ratio supply rejection ratio Power on threshold voltage, POR NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) EG(VDDmin))/VDDmax] Zero scale Full scale
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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