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Part: TLV5608IDWR
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description: ti TLV5608, 2.7V to 5.5V 10-Bit 8-channel Serial DAC
Company: Texas Instruments, Inc.
Datasheet: Download TLV5608IDWR datasheet File size : 3276 kB
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Datasheet text preview:
TLV5610, TLV5608, TLV5629 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS268C MAY 2000 REVISED DECEMBER 2000
features
applications
D D D D D D D D
Eight Voltage Output DACs in One Package TLV5610 . . . 12-Bit TLV5608 . . . 10-Bit TLV5629 . . . 8-Bit Programmable Settling Time vs Power Consumption 1 µs in Fast Mode 3 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Monotonic Over Temperature Low Power Consumption: 18 mW in Slow Mode at 3 V 48 mW in Fast Mode at 3 V Power Down Mode Buffered, High Impedance Reference Inputs Data Output for Daisy Chaining
D D D D D
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
DW OR PW PACKAGE (TOP VIEW)
DGND DIN SCLK FS PRE OUTE OUTF OUTG OUTH AGND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
DVDD DOUT LDAC MODE REF OUTD OUTC OUTB OUTA AVDD
description
The TLV5610, TLV5608, and TLV5629 are pin compatible eight channel 12-/10-/8-bit voltage output DACs each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs, and a data output which can be used to cascade multiple devices. The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be connected to the supply voltage. Implemented with a CMOS process, the DACs are designed for single supply operation from 2.7 V to 5.5 V. The devices are available in 20 pin SOIC and TSSOP packages.
AVAILABLE OPTIONS PACKAGE TA SOIC (DW) TLV5610IDW 40°C to 85°C TLV5608IDW TLV5629IDW TSSOP (PW) TLV5610IPW TLV5608IPW TLV5629IPW RESOLUTION 12 10 8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TLV5610, TLV5608, TLV5629 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS268C MAY 2000 REVISED DECEMBER 2000
functional block diagram
REF
12/10/8
12/10/8
12/10/8 X2
OUTA
DAC A Holding Latch SCLK DIN DOUT FS MODE PRE Serial Interface 12 8
DAC A Latch
DAC B, C, D, E, F, G and H Same as DAC A
OUT B, C, D, E, F, G and H
LDAC
Terminal Functions
TERMINAL NAME AGND AVDD DGND DIN DOUT DVDD FS LDAC MODE PRE REF SCLK OUTAOUTH NO. 10 11 1 2 19 20 4 18 17 5 16 3 1215, 69 I/O P P P I O P I I I I I I O Analog ground Analog power supply Digital ground Digital serial data input Digital serial data output Digital power supply Frame sync input Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input. DSP/µC mode pin. High = µC mode, NC = DSP mode. Preset input Voltage reference input Serial clock input DAC outputs A, B, C, D, E, F, G and H DESCRIPTION
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV5610, TLV5608, TLV5629 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS268C MAY 2000 REVISED DECEMBER 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, (AVDD, DVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage AVDD, AVDD voltage, AV AV High level digital input, VIH Low level digital input, VIL Reference voltage, Vref voltage Load resistance, RL Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA 40 5-V operation 3-V operation DVDD = 2.7 V to 5.5 V DVDD = 2.7 V to 5.5 V AVDD = 5 V AVDD = 3 V GND GND 2 100 30 85 4.096 2.048 4.5 2.7 2 0.8 AVDD AVDD TYP 5 3 MAX 5.5 3.3 UNIT V V V V V k pF MHz °C
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER IDD Power supply current supply current Power-down supply current POR PSRR Power on threshold Power supply rejection ratio Full scale, See Note 1 TEST CONDITIONS No load, , All inputs = DVDD or GND Vref = 4.096 V, , Fast Slow MIN TYP 16 6 0.1 2 60 MAX 21 8 UNIT mA µA V dB
NOTE 1: Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) EG(AVDDmin))/VDDmax]
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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