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Part: TM497EU9
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
-> Modules
-> 4 MB
-> FPM
Description: 4,194,304-word BY 9-bit DRAM Module (simm)
Company: Texas Instruments, Inc.
Datasheet: Download TM497EU9 datasheet File size : 199 kB
Request For quote: Find where to buy TM497EU9
Datasheet text preview:
TM497EU9 4 194 304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A FEBRUARY 1994 REVISED JUNE 1995
D D D D D D D D
Organization . . . 4 194 304 × 9 Single 5-V Power Supply (±10% Tolerance) 30-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes One 4-Megabit and Two 16-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2048 Cycles) All Inputs, Outputs, and Clocks Fully TTL Compatible 3-State Outputs Performance Ranges:
ACCESS ACCESS TIME TIME (tRAC) t(AA) (MAX) (MAX) 60 ns 30 ns 70 ns 35 ns 80 ns 40 ns ACCESS READ OR TIME WRITE (tCAC) CYCLE (MAX) (MIN) 15 ns 110 ns 18 ns 130 ns 20 ns 150 ns
U SINGLE-IN-LINE PACKAGE ( TOP VIEW )
D D D D D
'497EU9-60 '497EU9-70 '497EU9-80
Common CAS Control for Eight Common Data-In and Data-Out Lines Separate CAS Control for One Separate Pair of Data-In and Data-Out Lines Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Enhanced Page Mode Operation With CAS-Before-RAS ( CBR ), RAS-Only, and Hidden Refresh
VCC CAS DQ1 A0 A1 DQ2 A2 A3 VSS DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 A10 DQ6 W VSS DQ7 NC DQ8 Q9 RAS CAS9 D9 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
description
The TM497EU9 is a 4M-byte dynamic random-access memory (RAM) organized as 4 194 304 × 9 bits [bit nine (D9, Q9) is generally used for parity and is controlled by CAS9] in a 30-pin leadless single-in-line memory module (SIMM). The SIMM is composed of two TMS417400DJ, 4 194 304 × 4-bit dynamic RAMs, each in a 24/26-lead plastic small-outline J-lead (SOJ) package, and one TMS44100DJ, 4 194 304 × 1-bit dynamic RAM in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors.
PIN NOMENCLATURE A0 A10 CAS, CAS9 DQ1 DQ8 D9 NC Q9 RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out Data In No Connection Data Out Row-Address Strobe 5-V Supply Ground Write Enable
The TM497EU9 is available in the U single-sided, leadless module for use with sockets and is characterized for operation from 0°C to 70°C.
A0 A9 address lines must be refreshed every 16 ms.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
1
TM497EU9 4 194 304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A FEBRUARY 1994 REVISED JUNE 1995
operation
The TM497EU9 operates as two TMS417400DJs and one TMS44100DJ connected as shown in the functional block diagram (refer to the TMS417400 and TMS44100 data sheets for details of their operation). The common I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition, the ten least significant row addresses ( A0 A9) must be refreshed every 16 ms as required by the TMS44100. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR) cycle.
single-in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
A0 A10 RAS CAS W 11 4M × 4 A0 A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE 3 6 10 13 DQ1 DQ2 DQ3 DQ4
11
4M × 4 A0 A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE
16 20 23 25
DQ5 DQ6 DQ7 DQ8
11 CAS9
4M × 1 A0 A10 RAS CAS W
D Q
29 26
D9 Q9
2
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
TM497EU9 4 194 304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A FEBRUARY 1994 REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V °C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS CONDITIONS IOH = 5 mA IOL = 4.2 mA VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle '497EU9-60 MIN 2.4 0.4 ±10 ±10 325 MAX '497EU9-70 MIN 2.4 0.4 ±10 ±10 290 MAX '497EU9-80 MIN 2.4 0.4 ±10 ±10 260 MAX UNIT V V µA µA mA
ICC2
Standby current current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
6
6
6 mA
3
3
3
ICC3
Average refresh current (RAS-only or CBR) (see Note 3) Average page current (see Note 4)
325
290
260
mA
ICC4
210
180
150
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
3
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