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Part: TM497FBK32G
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
-> Modules
-> 16 MB
-> EDO
Description: 4,194,304 BY 32-bit Edo DRAM Module (simm)
Company: Texas Instruments, Inc.
Datasheet: Download TM497FBK32G datasheet File size : 199 kB
Request For quote: Find where to buy TM497FBK32G
Datasheet text preview:
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 FEBRUARY 1997
D D D D D D D D D D
Organization TM497FBK32R/G: 4 194 304 x 32 TM893GBK32R/G: 8 388 608 x 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets TM497FBK32R/G Uses Eight 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages TM893GBK32R/G Uses Sixteen 16M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 32 ms (2 048 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Extended Data Out (EDO) Operation With CAS-Before-RAS ( CBR ), RAS-Only, and Hidden Refresh
D D
Presence Detect Performance Ranges:
ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tA A tCAC tHPC (MAX) (MAX) (MAX) (MIN) '497FBK32R/G-50 50 ns 40 ns 20 ns 35 ns '497FBK32R/G-60 60 ns 30 ns 15 ns 25 ns '497FBK32R/G-70 70 ns 35 ns 18 ns 30 ns '893GBK32R/G-50 50 ns '893GBK32R/G-60 60 ns '893GBK32R/G-70 70 ns 40 ns 30 ns 35 ns 20 ns 15 ns 18 ns 35 ns 25 ns 30 ns
D D D D
Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Version Available: TM497FBK32G, TM893GBK32G Tin-Lead (Solder-) Tabbed Version Available: TM497FBK32R, TM893GBK32R
description
The TM497FBK32R/G, designed as 4 × 4 194 304 × 8-bits, is a 16M-byte, 72-pin, leadless, single-in-line memory module (SIMM). The SIMM is composed of eight (8) TMS417409DJs, 4 194 304 × 4-bit DRAMs, each in 24/26-lead, plastic, small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. See the TMS417409A data sheet (literature number SMKS893) for timing diagrams. The TM497FBK32R/G SIMM is available in the single-sided BK leadless module for use with sockets. The TM497FBK32R/G features RAS access times of 50, 60, and 70 ns. This device is designed for operation from 0°C to 70°C. The TM893GBK32R/G, designed as 4 × 8 388 608 × 8-bits, is a 32M-byte, 72-pin, leadless SIMM. The SIMM is composed of sixteen TMS417409DJs, 4 194 304 × 4-bit DRAMs, each in 24/26-lead, plastic, small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. See the TMS417409A data sheet (literature number SMKS893) for timing diagrams. The TM893GBK32R/G SIMM is available in the double-sided BK leadless module for use with sockets. The TM893GBK32R/G features RAS access times of 50, 60, and 70 ns. This device is characterized for operation from 0°C to 70°C.
operation
The TM497FBK32R / G operates as eight TMS417409DJs connected as shown in the functional block diagram of TM497RBK32R/G and in Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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· HOUSTON, TEXAS 772511443
1
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 FEBRUARY 1997
operation (continued)
The TM893GBK32R / G operates as sixteen TMS417409DJs connected as shown in the functional block diagram of TM893GBK32R/G and in Table 2. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VDD level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle.
2
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 FEBRUARY 1997
BK SINGLE-IN-LINE PACKAGE ( TOP VIEW )
TM497FBK32R/G ( SIDE VIEW )
TM893GBK32R/G ( SIDE VIEW )
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VD D NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VD D A8 A9 NC RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VD D DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 A10 CAS0 CAS3 DQ0 DQ31 NC PD1 PD4 RAS0 RAS3 VDD VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 70 ns TM497FBK32R/G 60 ns 50 ns 70 ns TM893GBK32R/G 60 ns 50 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) NC NC NC VSS VSS VSS PD3 (69) VSS NC NC VSS NC NC PD4 (70) NC NC VSS NC NC VSS
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
3
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