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Part: TM497MBK36H
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
-> Modules
-> 16 MB
-> FPM
Description: 4,194,304 BY 36-bit DRAM Module (simm)
Company: Texas Instruments, Inc.
Datasheet: Download TM497MBK36H datasheet File size : 199 kB
Request For quote: Find where to buy TM497MBK36H
Datasheet text preview:
TM497MBK36H, TM497MBK36I 4 194 304 BY 36-BIT DYNAMIC RAM MODULES
SMMS676 MARCH 1997
D D D D D D D D
Organization . . . 4 194 304 × 36 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Uses Eight 16M-bit Dynamic RAMs (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages and Four 4M-bit DRAMs in Plastic SOJ Packages Long Refresh Period . . . 32 ms (2 048 Cycles) All Inputs, Outputs, and Clocks are Fully TTL Compatible Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks Separate RAS Control for Eighteen Data-In and Data-Out Lines in Two Blocks
D D
3-State Output Performance Ranges:
ACCESS TIME tR A C (MAX) '497MBK36H / I-60 60 ns '497MBK36H / I-70 70 ns '497MBK36H / I-80 80 ns ACCESS ACCESS READ TIME TIME OR tC A C tA A WRITE CYCLE (MAX) (MAX) (MIN) 15 ns 18 ns 20 ns 30 ns 35 ns 40 ns 110 ns 130 ns 150 ns
D D D D D
Low Power Dissipation Operating Free-Air Temperature Range . . . 0°C to 70°C Presence Detect Gold-Tabbed Version Available TM497MBK36H Tin-Lead (Solder) Tabbed Version Available: TM497MBK36I
description
The TM497MBK36H / I is a 144M-bit dynamic random-access memory (DRAM) device organized as four times 4 194 304 × 9 (bit 9 generally is used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400ADJ, 4 194 304 × 4-bit DRAMs in 24/26-lead plastic SOJ packages, and four TMS44100DJ, 4 194 304 × 1-bit DRAMs in 20/26-lead plastic SOJ packages mounted on a substrate with decoupling capacitors. TMS417400ADJ and TMS44100DJ are described in the TMS417400A and TMS44100 data sheets (literature numbers SMKS889 and SMHS561, respectively). The TM497MBK36H / I is available in a double-sided, BK, leadless module for use with sockets. The TM497MBK36H / I features RAS access times of 60, 70, and 80 ns. This device is characterized for operation from 0°C to 70°C.
operation
The TM497MBK36H / I operates as eight TMS417400ADJs and four TMS44100DJs connected as shown in the functional block diagram and Table 1. See the TMS417400A and TMS44100 data sheets for details of operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. Table 1. Connection Table
DATA BLOCK DQ0 DQ8 DQ9 DQ17 DQ18 DQ26 DQ27 DQ35 RASx RAS0 RAS0 RAS2 RAS2 CASx CAS0 CAS1 CAS2 CAS3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. A0 A9 address lines must be refreshed every 16 ms.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
1
TM497MBK36H, TM497MBK36I 4 194 304 BY 36-BIT DYNAMIC RAM MODULES
SMMS676 MARCH 1997
BK SINGLE-IN-LINE PACKAGE ( TOP VIEW )
(SIDE VIEW )
VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VC C NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VC C A8 A9 NC RAS2 DQ26 DQ8 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VC C DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 A10 CAS0 CAS3 DQ0 DQ7, DQ9 DQ16, DQ18 DQ25, DQ27 DQ34 DQ8, DQ17, DQ26, DQ35 NC PD1 PD4 RAS0, RAS2 VCC VSS W Address Inputs Column-Address Strobe Data Input/Output Parity No Connection Presence Detect Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM497MBK36H/I 70 ns 60 ns PD1 (67) VSS VSS VSS PD2 (68) NC NC NC PD3 (69) NC VSS NC PD4 (70) VSS NC NC
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POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
TM497MBK36H, TM497MBK36I 4 194 304 BY 36-BIT DYNAMIC RAM MODULES
SMMS676 MARCH 1997
refresh The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS to retain data. Address line A10 must be used as the most significant refresh-address line (lowest frequency) to ensure correct refresh for both TMS417400A and TMS44100. A0 A9 address lines must be refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CAS-before-RAS [CBR]) cycle.
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497MBK36H: Nickel plate and gold plate over copper Contact area for TM497MBK36I: Nickel plate and tin-lead over copper
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
3
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