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Part: TMS28F033
Category:
Memory
-> SRAM
-> nvSRAM (Nonvolatile SRAM)
-> 4 Mb
Description: 4m Synchronous Nonvolatile Flash Memory
Company: Texas Instruments, Inc.
Datasheet: Download TMS28F033 datasheet File size : 612 kB
Request For quote: Find where to buy TMS28F033
Datasheet text preview:
TMS28F033 4 194 304-BIT SYNCHRONOUS FLASH MEMORY
SMJS833 NOVEMBER 1997
D D D D D D D D D D
DQ26 DQ27 VD D E VSSE DQ28 DQ29 DQ30 DQ31 A1 A0 A1 A2
13 14 15 16 17 18 19 20 21 22 23 24
52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DQ5 DQ4 VSSE VD D E DQ3 DQ2 DQ1 DQ0 NC NC NC A16
VSSI V PP
A10
A11
A3
A4
A5
A6
A7
A8
A9
A12
A14
V DDI
The TMS28F033 is the first synchronous nonvolatile flash memory device to offer a configurable burst interface to 16/32-bit microprocessors and microcontrollers operating at frequencies up to 40 MHz. The TMS28F033 contains 4M bits of main memory that is user-configurable as either three or four independently erasable blocks. In addition to the main memory array, there is a protected overlay memory block that is normally hidden from the memory address map. The following table shows the three- and four-block main-memory-array configurations for both 16-bit and 32-bit data bus widths. Table 1. Memory Configurations
DATA BUS WIDTH 16 bits 32 bits 3-BLOCK MAIN ARRAY 32K, 160K, and 64K 16K, 80K, and 32K 4-BLOCK MAIN ARRAY 32K, 96K, 64K, and 64K 16K, 48K, 32K, and 32K PROTECTED OVERLAY BLOCK 12K 6K
Embedded program and block-erase functions are fully automated by an on-chip write state machine (WSM), which simplifies these operations and relieves the system microcontroller of these secondary tasks. WSM status can be monitored by the on-chip status register to determine the progress of program/erase tasks.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
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A13
A15
description
1
ADVANCE INFORMATION
Organization 512K-Byte Main Array 24K-Byte Protected Overlay-Block User-Defined x16 or x32 Data Bus Read Transfer Data Rates Up to 100 MBytes / s at Bus Frequencies Up to 40 MHz Burstable Pipelined Read Interface With Programmable Latency, Length, and Order 10 000 Program / Erase Cycles Three Temperature Ranges Commercial . . . 0°C to 70°C Extended . . . 40°C to 85°C Automotive . . . 40°C to 125°C 80-Pin Plastic Quad Flatpack (PQFP) (PAF Suffix) Fully Automated On-Chip Erase and Program Operations Three Separate Voltage Supplies I / O Supply Configurable 3.3 V / 5 V Read Supply 5 V Programming Supply 12 V All Inputs / Outputs TTL-Compatible
PAF 80-PIN PACKAGE (T0P VIEW)
WORD/DIS
BAA/LRV
RY/BY
OE
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DQ16 DQ17 DQ18 DQ19 VD D E VSSE DQ20 DQ21 DQ22 DQ23 DQ24 DQ25
1 2 3 4 5 6 7 8 9 10 11 12
V DDE
64 63 62 61 60 59 58 57 56 55 54 53
S/5IO
V DDI
V SSI
LBO
CLK
LBA
WR
WE
QV
RP
E
DQ15 DQ14 DQ13 DQ12 VSSE VD D E DQ11 DQ10 DQ9 DQ8 DQ7 DQ6
TMS28F033 4 194 304-BIT SYNCHRONOUS FLASH MEMORY
SMJS833 NOVEMBER 1997
description (continued)
The TMS28F033 flash memory requires 12 V for erasure and programming, and 5 V for memory-array access while interfacing with either a 3.3-V or 5-V bus. The TMS28F033 flash memory is fabricated using CMOS technology and is packaged in an 80-pin plastic quad flatpack (PQFP) (PAF suffix).
device symbol nomenclature
TMS28F033 X B PAF Q
ADVANCE INFORMATION
Temperature Range L (Commercial) = 0°C to 70°C E (Extended) = 40°C to 85°C Q (Automotive) = 40°C to 125°C Package Type PAF = 80-Pin Plastic Quad Flatpack
Program/Erase Endurance B= 10 000 Cycles
Speed Option 25 = 25 MHz 33 = 33 MHz
2
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TMS28F033 4 194 304-BIT SYNCHRONOUS FLASH MEMORY
SMJS833 NOVEMBER 1997
functional block diagram
DQ0 DQ7, DQ24 DQ31 DQ8 DQ23
CLK Output Buffer Output Buffer Input Buffer Input Buffer Control Logic and Clocks E OE WE LBA WR DIS Default Configuration Burst State Machine Device Configuration Register Data Input Register RP 3/5IO
LBO QV OE / BAA WORD
Read Latch
Write Latch Data Input Register Output Register IP Register Output Register Status Register
Command State Machine
A1
Input Buffer
A0 A16
Input Buffer Data Comparator
Write State Machine
LRV
RY / BY Read Address Counter Address MUX Write Address Counter Program / Erase Voltage Switch
Y Decoder 24K-Byte Overlay Block
Y Gating/Sensing
VPP
X Decoder
512K-Byte Main Block
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3
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