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Part: TMS426400P-60
Category:
Memory
-> DRAM
Description: ti TMS426400, 4194304-Word BY 4-Bit High-speed DRAMs
Company: Texas Instruments, Inc.
Datasheet: Download TMS426400P-60 datasheet File size : 1495 kB
Request For quote: Find where to buy TMS426400P-60
Datasheet text preview:
TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4 194 304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B MAY 1995 REVISED AUGUST 1995
D D D D
Electrical characteristics for TMS416400/P and TMS417400 / P is Production Data. Electrical characteristics for TMS426400/P and TMS427400 / P is Product Preview only. Organization . . . 4 194 304 × 4 Single 5 V Power Supply for TMS41x400 / P (±10% Tolerance) Single 3.3 V Power Supply for TMS42x400 / P (± 0.3 V Tolerance) Performance Ranges:
ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tC A C tA A CYCLE MAX MAX MAX MIN 60 ns 15 ns 30 ns 110 ns 70 ns 18 ns 35 ns 130 ns 80 ns 20 ns 40 ns 150 ns
DJ PACKAGE ( TOP VIEW )
DGA PACKAGE ( TOP VIEW )
VC C DQ1 DQ2 W RAS A11 A10 A0 A1 A2 A3 VC C
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS
VCC DQ1 DQ2 W RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS
D D D D D
'4xx400/P-60 '4xx400/P-70 '4xx400/P-80
D D
Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR ) Refresh Long Refresh Period and Self-Refresh Option ( TMS4xx400P) 3-State Unlatched Output Low Power Dissipation High-Reliability Plastic 24 / 26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package and 24 / 26-Lead Surface-Mount Thin Small-Outline Package ( TSOP) Operating Free-Air Temperature Range: 0°C to 70°C EPICTM (Enhanced Performance Implanted CMOS) Technology
PIN NOMENCLATURE A0 A11 CAS DQ1 DQ4 OE NC RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out Output Enable No Internal Connection Row-Address Strobe 5-V or 3.3-V Supply Ground Write Enable
A11 is NC for TMS4x7400 / P. See Available Options Table
description
The TMS4xx400 is a set of high-speed, 16 777 216-bit dynamic random-access memories organized as 4 194 304 words of 4 bits each. The TMS4xx400P series are high-speed, low-power, self-refresh, 16 777 216-bit dynamic randomaccess memories organized as 4 194 304 words of 4 bits each. The TMS4xx400 and TMS4xx400P employ state-of-the-art EPICTM (Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power.
DEVICE
AVAILABLE OPTIONS POWER SUPPLY 5V 5V 5V 5V 3.3 V 3.3 V 3.3 V 3.3 V SELF REFRESH BATTERY BACKUP -- Yes -- Yes -- Yes -- Yes REFRESH CYCLES 4096 in 64 ms 4096 in 128 ms 2048 in 32 ms 2048 in 128 ms 4096 in 64 ms 4096 in 128 ms 2048 in 32 ms 2048 in 128 ms
TMS416400 TMS416400P TMS417400 TMS417400P TMS426400 TMS426400P TMS427400 TMS427400P
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443
Copyright © 1995, Texas Instruments Incorporated
· HOUSTON, TEXAS 772511443
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TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4 194 304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B MAY 1995 REVISED AUGUST 1995
description (continued)
The TMS4xx400 and TMS4xx400P are each offered in a 24 / 26-lead plastic surface-mount TSOP (DGA suffix) package and a 24 / 26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized for operation from 0°C to 70°C.
operation
enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP, the maximum RAS low time. Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCPA or tCAC. address: A0 A11 ( TMS4x6400 / P) and A0 A10 (TMS4x7400 / P) Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. For the TMS4x6400 and TMS4x6400P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. write enable ( W ) The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. data in (DQ1 DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ1 DQ4) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied.
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POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4 194 304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B MAY 1995 REVISED AUGUST 1995
RAS-only refresh
TMS4x6400, TMS4x6400P
A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This can be achieved by strobing each of the 4096 rows (A0 A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh.
TMS4x7400, TMS4x7400P
A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This can be achieved by strobing each of the 2048 rows (A0 A10). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS-before-RAS ( CBR ) refresh CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. battery-backup refresh
TMS4x6400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V ) or 350 µA (3.3 V ) refresh current is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25 µs while holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels ( VIL VCC 0.2 V ).
TMS4x7400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V ) or 350 µA (3.3 V ) refresh current is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5 µs while holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels ( VIL VCC 0.2 V ). self refresh ( TMS4xx400P) The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures the DRAM is fully refreshed. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh ( RAS-only or CBR ) cycle.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
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