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Part: TMS427809AP
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
-> 16 Mb
-> Asynchronous->5V EDO
Description: 2 097 152 BY 8-bit Edo DRAM
Company: Texas Instruments, Inc.
Datasheet: Download TMS427809AP datasheet File size : 1495 kB
Request For quote: Find where to buy TMS427809AP
Datasheet text preview:
TMS417809A, TMS427809A, TMS427809AP 2 097 152 BY 8-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B AUGUST 1996 REVISED NOVEMBER 1997
D D D
This data sheet is applicable to all TMS417809As and TMS427809A/Ps symbolized by Revision "E" and subsequent revisions as described in the device symbolization section. Organization . . . 2 097 152 by 8 Bits Single Power Supply (5 V or 3.3 V) Performance Ranges:
ACCESS ACCESS ACCESS TIME TIME TIME tR A C tCAC tAA MAX MAX MAX 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns EDO CYCLE tHPC MIN 20 ns 25 ns 30 ns 20 ns 25 ns 30 ns
DZ / DGC PACKAGE ( TOP VIEW )
D D D D D
'417809A-50 '417809A-60 '417809A-70 '427809A/P-50 '427809A/P-60 '427809A/P-70
D
Extended-Data-Out (EDO) Operation CAS-Before-RAS ( CBR ) Refresh Long Refresh Period and Self-Refresh Option (TMS427809AP) High-Impedance State Unlatched Output High-Reliability Plastic 28-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) and 28-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGC Suffix) Ambient Temperature Range 0°C to 70°C
VCC DQ0 DQ1 DQ2 DQ3 W RAS NC A10 A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS
PIN NOMENCLATURE A[0 :10] DQ[0: 7] CAS NC OE RAS VCC VSS W Address Inputs Data In / Data Out Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe 3.3-V or 5-V Supply Ground Write Enable
description
The TMS417809A and TMS427809A series are 16 777 216-bit dynamic random access memory (DRAM) devices organized as 2 097 152 words of 8 bits each. The TMS427809AP series is a low-power, self-refresh, 16 777 216-bit DRAM organized as 4 194 304 words of four bits.They employ TI state-of-the-art technology for high performance, reliability, and low power.
AVAILABLE OPTIONS DEVICE TMS417809A TMS427809A TMS427809AP POWER SUPPLY 5V 3.3 V 3.3 V REFRESH CYCLES 2 048 in 32 ms 2 048 in 32 ms 2 048 in 128 ms
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS417809A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). The TMS427809A / P is offered in a 28-lead plastic surface-mount TSOP package (DGC suffix). These packages are designed for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
TMS417809A, TMS427809A, TMS427809AP 2 097 152 BY 8-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B AUGUST 1996 REVISED NOVEMBER 1997
logic symbol (TMS417809A and TMS427809A/P)
RAM 2M x 8 A0 10 A1 11 A2 12 A3 13 A4 16 A 0 2 097 151 A5 17 A6 18 A7 19 A8 20 A9 21 A10 9 20D19/21D9 20D20 C20[ROW] RAS 7 G23/[REFRESH ROW] 24[PWR DWN] C21[COL] G24 & 23C22 W6 OE 22 23,21D G25 A,22D 26 DQ1 3 DQ2 4 DQ3 5 DQ4 24 DQ5 25 DQ6 26 DQ7 27 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. 24,25EN 20D10/21D0
CAS 23
DQ0 2
A,Z26
2
POST OFFICE BOX 1443
· HOUSTON, TEXAS 772511443
TMS417809A, TMS427809A, TMS427809AP 2 097 152 BY 8-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B AUGUST 1996 REVISED NOVEMBER 1997
functional block diagram (TMS417809A and TMS427809A/P)
RAS CAS W OE
Timing and Control
A0 A1 Column Address Buffers A9
10
Column Decode Sense Amplifiers 256K Array 256K Array R o w D e c o d e 256K Array 11 256K Array 256K Array 256K Array 8 32 I/O Buffers DataIn Reg. DataOut Reg. 8 8 8
32 Row Address Buffers A10 11
DQ0 DQ7
operation
extended data out Extended data out (EDO) allows data output rates up to 50 MHz for 50-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup-and-hold and for address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the maximum RAS low time. The EDO does not place the data-in / data-out pins (DQ pins) in the high-impedance state with the rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO operation benefits. address: A0 A10 Twenty-one address bits are required to decode each of the 2 097 152 storage-cell locations. Eleven row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip-enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip-select, activating the output buffers and latching the address bits into the column-address buffers. output-enable (OE) OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two methods of placing the DQs into the high-impedance state and maintaining that state during CAS high time. The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions on OE until CAS falls again (see Figure 8).
POST OFFICE BOX 1443
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