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Details, datasheet, quote on part number:TPS2330ID
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| Part: | TPS2330ID |
| Category: | Power Management => Power Distribution/Switches => Hot-Swap Controllers => External FET |
| Description: | ti TPS2330, 3-13V Single Hot-swap ic w/ Power Good Report, Act-low Enable |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download TPS2330ID datasheet File size : 358 kB |
| Request For quote: | Find where to buy TPS2330ID
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Datasheet text preview:
TPS2330, TPS2331 SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277D MARCH 2000 REVISED SEPTEMBER 2001
features
D D D D D D D D D D D D D
D OR PW PACKAGE (TOP VIEW)
Single-Channel High-Side MOSFET Driver Input Voltage: 3 V to 13 V Inrush Current Limiting With dv/dt Control Circuit-Breaker Control With Programmable Current Limit and Transient Timer Power-Good Reporting With Transient Filter CMOS- and TTL-Compatible Enable Input Low 5-µA Standby Supply Current . . . Max Available in 14-Pin SOIC and TSSOP Package 40°C to 85°C Ambient Temperature Range Electrostatic Discharge Protection
GATE DGND TIMER VREG VSENSE AGND ISENSE
1 2 3 4 5 6 7
14 13 12 11 10 9 8
DISCH ENABLE PWRGD FAULT ISET AGND IN
NOTE: Terminal 13 is active high on TPS2331.
typical application
VO + VIN 3 V 13 V IN VREG ISET ISENSE GATE DISCH VSENSE
applications
Hot-Swap/Plug/Dock Power Management Hot-Plug PCI, Device Bay Electronic Circuit Breaker
AGND DGND
TPS2330
PWRGD FAULT TIMER
ENABLE
description
The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and separation of load transients from actual load increases, are critical requirements for hot-swap applications. The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS TA HOT-SWAP CONTROLLER DESCRIPTION CONTROLLER DESCRIPTION Dual-channel with independent OCP and adjustable PG Dual-channel with interdependent OCP and adjustable PG 40°C to 85°C Dual-channel with independent OCP Single-channel with OCP and adjustable PG PIN COUNT 20 20 16 14 PACKAGES ENABLE TPS2300IPW TPS2310IPW TPS2320ID TPS2320IPW TPS2330ID TPS2330IPW ENABLE TPS2301IPW TPS2311IPW TPS2321ID TPS2321IPW TPS2331ID TPS2331IPW
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TPS2330, TPS2331 SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277D MARCH 2000 REVISED SEPTEMBER 2001
functional block diagram
IN VREG PREREG ISET ISENSE GATE Clamp dv/dt Rate Protection 50 µA UVLO and Power-Up Circuit Breaker Charge Pump Pulldown FET Circuit Breaker 75 µA 20-µs Deglitch DISCH
AGND
VSENSE PWRGD
DGND
ENABLE
50-µs Deglitch
Logic
FAULT
TIMER
Terminal Functions
TERMINAL NAME AGND DGND DISCH ENABLE/ ENABLE FAULT GATE IN ISENSE ISET PWRGD TIMER VREG VSENSE NO. 6,9 2 14 13 11 1 8 7 10 12 3 4 5 I/O I I O I O O I I I O O O I DESCRIPTION Analog ground, connects to DGND as close as possible Digital ground Discharge transistor Active low (TPS2330) or active high enable (TPS2331) Overcurrent fault, open-drain output Connects to gate of high-side MOSFET Input voltage Current-sense input Adjusts circuit-breaker threshold with resistor connected to IN Open-drain output, asserted low when VSENSE voltage is less than reference. Adjusts circuit-breaker deglitch time Connects to bypass capacitor, for stable operation Power-good sense input
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPS2330, TPS2331 SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277D MARCH 2000 REVISED SEPTEMBER 2001
detailed description
DISCH DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-voltage connection for internal gate-voltage-clamp circuitry. ENABLE or ENABLE ENABLE for TPS2330 is active low. ENABLE for TPS2331 is active high. When the controller is enabled, GATE voltage will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA. FAULT FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back on, either the enable pin has to be toggled or the input power has to be cycled. GATE GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend upon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source voltages of 9 V12 V across the external MOSFET transistor. IN IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation. ISENSE, ISET ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. An internal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET. PWRGD PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD is active low to indicate an undervoltage condition on the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pull-up power supply rail in disable mode. TIMER A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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