|Category||Semiconductors => Power Management => Power Over Ethernet (PoE)/LAN Solutions => Powered Device|
|Part family||TPS23750 IEEE 802.3af PD Controller with Integrated DC/DC|
|Description||IEEE 802.3af PD Controller with Integrated DC/DC 20-HTSSOP -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TPS23750 datasheet
|Cross ref.||Similar parts: LTC3833EFE#PBF, LTC3833EFE#TRPBF, LTC3833IFE#PBF, LTC3833IFE#TRPBF, LTC3834EFE#PBF, LTC3834EFE#TRPBF, LTC3834IFE#PBF, LTC3834IFE#TRPBF, LTC3835EFE, LTC3835EFE#PBF|
|PoE Current Limit(Min)(mA)||405|
|PD Power Level||13W|
|PoE Standards Supported||802.3at Type 1 (802.3af)|
|Special Features||Error Amplifier,Thermal Shutdown|
|Approx. Price (US$)||1.25 | 1ku|
|DC/DC Control||PD and DC/DC|
|Fault Response||Auto Retry|
|PoE Inrush Limit(Typ)(mA)||140|
|rDS(on) per FET(Typ)(mOhms)||600|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Designing an EMI Compliant PoE with Isolated Flyback | Doc|
|• Lightning Surge Considerations for PoE Powered Devices | Doc|
|• Wall Adapter Powers IEEE 802.3af Powered Device
Power-on-Ethernet is an emerging technology that allows an existing Ethernet connection to carry both data and power. However, today's powered-device (PD) designers face a dilemma - not all Ethernet connections are wired for power. To operate with these le | Doc
|• Bridging the Efficiency Gap in PoE Powered Device Designs
The trend toward higher efficiency is becoming increasingly evident for Power over Ethernet (PoE) applications. Powered Device (PD) suppliers are looking for solutions that enable them to market their products as being â€śGreenâ€ť or energy efficient. All | Doc
|• Practical Guidelines EMI Compliant PoE
Practical Guidelines to Designing an EMI Compliant PoE Powered Device with Non-Isolated DC/DC | Doc
|TPS23750EVM-107: TPS23750 Evaluation Module Buck|
|TPS23750EVM-108: TPS23750 Evaluation Module Flyback|
Complete 802.3af PoE Interface Features derived from the V, 0.6 Internal Pass MOSFET Standard and Legacy UVLO Choices Fixed 140 mA Inrush Limit Primary Side DC/DC Converter Control Minimum External Component Count Current Mode Control Isolated and Non-Isolated Topologies Programmable Operating Frequency Current Sense Leading-edge Blanking 50% Duty Cycle Limiting Voltage Output Error Amplifier Internal PoE and Converter Sequencing Industry-Standard 20 Lead Package Industrial Temperature Range: to 85°CDESCRIPTION
The TPS23750 integrates the functionality of the TPS2375 with a primary-side dc/dc PWM controller. The designer can create a front-end solution for PoE-PD applications with minimum external components. The TPS23770 is identical to the TPS23750 with the exception of the undervoltage lockout turn-on voltage, which is compatible with legacy systems. The PoE front end has all the necessary IEEE 802.3af functions including detection, classification, undervoltage lockout and inrush control. The PoE input switch is integrated within the TPS23750. The dc/dc controller section is designed to support flyback, forward, and nonsynchronous low-side switch buck topologies. The external switching MOSFET and current sense resistor provide flexibility in topology, power level, and current limit. The full-featured dc/dc controller includes programmable soft start, hiccup type fault limiting, 50% maximum duty cycle, programmable constant switching frequency, and a true voltage-output error amplifier. Additional protection features provide for robust designs.APPLICATIONS
All PoE PD Devices Including: Wireless Access Points VoIP Phones Security Cameras
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
(1) (2) UVLO THRESHOLDS TYPE Standard Legacy LOW 30.5 V HIGH 35.1 V PACKAGE (2) TSSOP-20 PowerPADTM TPS23750PWP TPS23770PWP MARKING TPS23750 TPS23770
Add an R suffix to the device type for tape and reel. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com.over operating free-air temperature range and with respect to VSS unless otherwise noted (1)
UNIT Input voltage range (2) Input voltage range Input voltage range (3) Input voltage range Input voltage range Input voltage range (3) Sourcing current VBIAS Sourcing current Sourcing or sinking current, COMP Average sourcing or sinking current, GATE HBM ESD rating ESD system level (contact/air) at RJ-45 Continuous total power dissipation TJ Tstg Maximum operating junction temperature Storage temperature range Lead temperature 1.6mm (1/16-inch) from case for 10 seconds
RSN, COM, RTN, SEN AUX, VDD, DET, SENP [VBIAS, BL, TMR, FB, COMP, FREQ, RSP, MODE] to RTN [GATE or AUX] to COM [RSN to RTN] and [COM to RTN] SENP to SEN CLASS AUX
12 V Internally limited Internally limited Internally limited 25 mArms 15 kV See Dissipation Rating Table Internally limited 150°C 260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. IRTN = 0 for VRTN 80 V. Maximum IRTN V. Do not apply external voltage sources to CLASS, DET, GATE, FREQ, VBIAS, and TMR. Surges applied RJ-45 of Figure 40 between pins of RJ-45, and between pins and output voltage rails per EN61000-4-2, 1999 with no device failure.All voltage values are with respect to VSS unless otherwise noted.
MIN VDD Input voltage range (3) Input voltage range COM, SEN, SENP FB, COMP, MODE, BL AUX to COM RSP to RSN AUX Sourcing current QG GATE loading AUX load capacitance VBIAS load capacitance RFREQ (2) (3) Operating junction temperature range Operating ambient temperature range VBIAS COMP NOM MAX 67 VBIAS mA V UNIT V
RSN, COM, and RTN should be tied together. SENP should be tied to VDD except for the buck configuration, where it should be tied to the output positive rail. TMR, FREQ, CLASS, DET, VBIAS, and GATE should not be externally driven. Junction temperature may be a constraining factor for high bias power designs.
PACKAGE PWP (TSSOP-20) JP °C/W 1.4 JC °C/W 26.62 JA °C/W 32.6 JA °C/W 151.9 JA °C/W (4) 73.8 MAXIMUM POWER RATING (W) (5) 1.2
Thermal resistance junction to pad. See TI document SLMA002 for recommended layout. This is a best case, zero airflow number. JEDEC method with low-k board (2 signal layers) and power pad not soldered (worst case). JEDEC method with high-k board (4 layers, 2 signal and 2 planes) and power pad not soldered. Based on TI recommended layout and 85°C ambient.
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