Details, datasheet, quote on part number: TPS3808G50DBVT
CategorySemiconductors => Power Management => Supervisor and Reset IC
Part familyTPS3808 Low Quiescent Current, Programmable-Delay Supervisory Circuit
DescriptionLow Quiescent Current, Programmable-Delay Supervisory Circuit 6-SOT-23 -40 to 125
CompanyTexas Instruments, Inc.
DatasheetDownload TPS3808G50DBVT datasheet
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Threshold Voltage 1(Typ)(V)Adjustable,0.84,1.12,1.16,1.4,1.67,1.77,2.33,2.79,3.07,4.65
Output Driver Type / Reset OutputActive-low,Open-drain
Reset Threshold Accuracy(%)2
Operating Temperature Range(C)-40 to 125
# of Supplies Monitored1
Watchdog Timer WDI(sec)None
Approx. Price (US$)0.68 | 1ku
Monitored Voltage 1 (typ)(Nom)(V)Adjustable,0.9,1.2,1.25,1.5,1.8,1.9,2.5,3,3.3,5
Package GroupSOT-23,WSON
Time Delay(ms)Programmable
Monitored Voltage 2 (typ)(Nom)(V)N/A
Threshold Voltage 2 (typ)(Typ)(V)N/A
FeaturesActive Low Enable,Manual Reset
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
Application notes
• Setting the SVS Voltage Monitor Threshold | Doc
• Recommended Power Solutions for the TMS320x2810/1/2 DSPs
This application report provides a table to assist users in selecting the best power solution for their specific TMS320281x application. | Doc
• Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices
This reference design is intended to help designers wishing to use two of the new Virtex-6™ LX240 FPGA along with DDR memory and other optional circuitry in their designs. It provides nine rails of lower voltage with an input of 12 volts. The use | Doc
• Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs | Doc
Evaluation Kits
SN65DSI85Q1-EVM: Dual-Channel MIPIĀ® DSI to Dual-Link FlatLinkĀ™ LVDS Bridge Evaluation Module
SN65DSI85EVM: SN65DSI85 Dual-Channel MIPIĀ® DSI to Dual-Link FlatLinkĀ™ LVDS Bridge Evaluation Module
TDP158RSBEVM: 6 Gbps AC Coupled to TMDSĀ™/HDMIĀ™ Redriver Evaluation Module
SN65DSI83Q1-EVM: MIPIĀ® DSI to FlatLinkĀ™ LVDS Bridge Evaluation Module
Spice Model
TPS3808G01 TINA-TI Transient Spice Model - ZIP (05/12/2011)
TPS3808G01 PSpice Transient Model (Rev. A) - ZIP (06/03/2011)


Features, Applications


Power-On Reset Generator with Adjustable Delay Time: to 10s Very Low Quiescent Current: 2.4-µA typ High Threshold Accuracy: 0.5% typ Fixed Threshold Voltages from 5 V and Adjustable Voltage Down 0.4 V Are Available Manual Reset (MR) Input Open-Drain RESET Output Temperature Range: to 125°C Small SOT23 Package


The TPS3808xxx family of microprocessor supervisory circuits monitor system voltages from 5.0 V, asserting an open drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and manual reset (MR) return above their thresholds. The TPS3808 uses a precision reference to achieve 0.5% threshold accuracy for VIT 3.3V. The reset delay time can be set 20ms by disconnecting the CT pin, 300ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted between 1.25ms and 10s by connecting the CT pin to an external capacitor. The TPS3808 has a very low typical quiescent current it is well-suited to battery-powered applications. It is available in a small SOT23 package and is fully specified over a temperature range to 125°C.


DSP or Microcontroller Applications Notebook/Desktop Computers PDAs/Hand-Held Products Portable/Battery-Powered Products FPGA/ASIC Applications

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION

PRODUCT NOMINAL SUPPLY VOLTAGE (1) Adjustable 3.3V 5.0V THRESHOLD VOLTAGE (VIT) 3.07V 4.65V SPECIFIED TEMPERATURE RANGE to +125°C PACKAGE MARKING AVW AVV AVY AVS AVR AVQ AVP AVO AVN ORDERING NUMBER TPS3808G50DBVT TPS3808G50DBVR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000 Tape and Reel, 250 Tape and Reel, 3000

Custom threshold voltages from 5.0 V are available on a quick-turn basis for fast prototyping. Minimum order quantities apply. Contact factory for details and availability. Available July, 2004.

over operating junction temperature range (unless otherwise noted) (1)

TPS3808 Input voltage range, VDD CT voltage range, VCT Other voltage ranges: VRESET, VMR, VSENSE RESET pin current Operating junction temperature range, TJ (2) Storage temperature range, TSTG ESD rating, HBM ESD rating, CDM -0.3 to VDD 2 500 UNIT kV V

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Due to the low dissipated power in this device, it is assumed that TJ = TA.

1.8 V VDD 6.5 V, RLRESET 100 k, CLRESET = 50 pF, over operating temperature range (TJ to +125°C), unless otherwise noted. Typical values are = 25°C.

PARAMETER VDD IDD Input supply range VDD 3.3 V, RESET not asserted MR, RESET, CT open VDD 6.5 V, RESET not asserted MR, RESET, CT open 1.3 V VDD 1.8 V, IOL 1.8 V VDD 6.5V, IOL 1.0 mA VOL (max) 0.2 V, IRESET 15µA TPS3808G01 VIT V < VIT 5.0 V VSENSE = VIT VSENSE 6.5 V VRESET 6.5 V, RESET not asserted CT pin Other pins VIN V to VDD VIN V 0.3 VDD 0.7 VDD SENSE CT = Open td RESET delay time CT = VDD 180 nF Propagation delay tpHL JA (1) High to low level RESET delay Thermal resistance, junction-to-ambient The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) 15 µs/V. MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD See timing diagram VIH = 1.05 VIT, VIL = 0.95 VIT VIH = 0.7 VDD, VIL = 0.3 VDD TPS3808G01 Fixed versions TEST CONDITIONS MIN 2.4 2.7 TYP MAX %VIT ns µs °C/W % UNIT µA V

Low-level output voltage Power-up reset voltage (1)

MR Internal pull-up resistance Input current at SENSE pin RESET leakage current Input capacitance, any pin MR logic low input MR logic high input Maximum transient duration


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