|Category||Semiconductors => Power Management => Supervisor and Reset IC|
|Part family||TPS3813 Processor Supervisory Circuit with Window-Watchdog Timer|
|Description||Processor Supervisory Circuit with Window-Watchdog Timer 6-SOT-23 -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TPS3813I50DBVR datasheet
|Output Driver Type / Reset Output||Active-low,Open-drain|
|Operating Temperature Range(C)||-40 to 85|
|Reset Threshold Accuracy(%)||2.2|
|Watchdog Timer WDI(sec)||Programmable|
|# of Supplies Monitored||1|
|Threshold Voltage 1(Typ)(V)||2.25,2.64,2.93,4.55|
|Approx. Price (US$)||0.75 | 1ku|
|Monitored Voltage 1 (typ)(Nom)(V)||2.5,3,3.3,5|
|Monitored Voltage 2 (typ)(Nom)(V)||N/A|
|Threshold Voltage 2 (typ)(Typ)(V)||N/A|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs | Doc|
Window-Watchdog With Programmable Delay and Window Ratio 6-Pin SOT-23 Package Supply Current 9 µA (Typ) Power On Reset Generator With a Fixed Delay Time 25 ms Precision Supply Voltage Monitor 5 V Open-Drain Reset Output Temperature Range. to 85°C
Applications Using DSPs, Microcontrollers, or Microprocessors Safety Critical Systems Automotive Systems Heating Systemsdescription
The TPS3813 family of supervisory circuits provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems.
During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. There after, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider. For safety critical applications the TPS3813 family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813 within this window not to assert a RESET.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
The product spectrum is designed for supply voltages 3.3 V, and 5 V. The circuits are available 6-pin SOT23 package. The TPS3813 devices are characterized for operation over a temperature range to 85°C.
PACKAGE INFORMATION TA DEVICE NAME TPS3813K33DBV TPS3813I50DBV THRESHOLD VOLTAGE 4.55 V MARKING PCDI PEZI PFAI PFBI
J 25 DBV R Reel Package Nominal Supply Voltage Nominal Threshold Voltage Functionality Family TPS3813 FUNCTION/TRUTH TABLE VDD > VIT 0 1 RESET L H
RESET WDT Oscillator Reset Logic and Timer Detection Circuit VDD _ R2 Bandgap Voltage Reference Rising Edge Detection Power to circuitry Watchdog Ratio Detection
2nd Window With Lower Boundary 3rd Window With Lower Boundary Trigger Pulse 1st Window Lower Window Without Lower 2nd Window 1st Window Boundary With Lower Without Lower Boundary 3rd Window With Lower Boundary
The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the different oscillator frequency. This is described in more detail in the following section. The timing diagram and especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description.
TERMINAL NAME GND RESET VDD WDI WDR WDT NO. I/O Ground Open-drain reset output Supply voltage and supervising input Watchdog timer input Selectable watchdog window ratio input Programmable watchdog delay input DESCRIPTION
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