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Part: TPS70145PWP
Category:
Power Management
-> Regulators
-> Linear Regulators
-> LDO (Low Drop Out)
Description: ti TPS70145, Dual-output LDO Voltage Regulators
Company: Texas Instruments, Inc.
Datasheet: Download TPS70145PWP datasheet File size : 1862 kB
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Datasheet text preview:
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222B DECEMBER 1999 REVISED OCTOBER 2002
D Dual Output Voltages for Split-Supply D D D D D
Applications Selectable Power Up Sequencing for DSP Applications (See Part Number TPS702xx for Independently Enabled Outputs) Output Current Range of 500 mA on Regulator 1 and 250 mA on Regulator 2 Fast Transient Response Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset With 120-ms Delay
D D D D D D D D D D
Open Drain Power Good for Regulator 1 Ultralow 190 µA (typ) Quiescent Current 1-µA Input Current During Standby Low Noise: 65 µVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 20-Pin PowerPAD TSSOP Package Thermal Shutdown Protection
PWP PACKAGE (TOP VIEW)
description
TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and enable function, provide a complete system solution.
TPS70151 PWP 5V 0.1 µF VIN1 VOUT1 VSENSE1 PG1 VIN2 0.1 µF MR2 MR2 >2 V 2 V <0.7 V VSENSE2 SEQ VOUT2 10 µF 10 µF
NC VIN1 VIN1 MR1 MR2 EN SEQ GND VIN2 VIN2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC VOUT1 VOUT1 VSENSE1/FB1 PG1 RESET VSENSE2/FB2 VOUT2 VOUT2 NC
3.3 V
DSP
I/O
250 k PG1
250 k RESET
>2 V
EN <0.7 V
EN
MR1
1.8 V
Core
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and TMS320 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222B DECEMBER 1999 REVISED OCTOBER 2002
description (continued)
The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10 uF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500 mA, and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. over load condition) VOUT1 is turned off. Pulling the SEQ terminal low, reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off(disabled). The PG1 pin reports the voltage conditions at the VOUT1, which can be used to implement a SVS for the circuitry supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of the VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after 120 ms delay. RESET goes to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e. over load condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until VIN1 reaches 2.5 V.
AVAILABLE OPTIONS TJ REGULATOR 1 VO (V) 3.3 V 3.3 V 40°C to 125°C to 125°C 3.3 V 3.3 V Adjustable (1.22 V to 5.5 V) REGULATOR 2 VO (V) 1.2 V 1.5 V 1.8 V 2.5 V Adjustable (1.22 V to 5.5 V) TSSOP (PWP) TPS70145PWP TPS70148PWP TPS70151PWP TPS70158PWP TPS70102PWP
NOTE: The TPS70102 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70102PWPR).
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222B DECEMBER 1999 REVISED OCTOBER 2002
detailed block diagram fixed voltage version
VIN1 (2 Pins) Current Sense 10 k ENA_1 VSENSE1 (see Note A) VOUT1 (2 Pins)
UVLO V_UVLO GND Shutdown
Reference Thermal Shutdown Vref Vref
+
ENA_1 FB1
PG1 FB1 0.95 × Vref Rising Edge Deglitch VIN1
Shutdown UV Comp FB2 0.83 × Vref FB1 0.83 × Vref UV Comp EN VC C Falling Edge Deglitch FB2 0.95 × Vref Power Sequence Logic ENA_1 ENA_2
MR2 PG1 Comp Rising Edge Deglitch Falling Edge Delay VIN1 RESET
Falling Edge Deglitch
Vref
FB2
MR1
+
ENA_2 ENA_2 10 k VOUT2(2 Pins) VSENSE2 (see Note A)
SEQ (see Note B) VIN2 (2 Pins)
Current Sense
NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the application information section. B. If the SEQ terminal is floating at the input, the VOUT2 powers up first.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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