|
|
Part: TPS70345
Category:
Power Management
-> Regulators
-> Linear Regulators
-> LDO (Low Drop Out)
Description:
Company: Texas Instruments, Inc.
Datasheet: Download TPS70345 datasheet File size : 1862 kB
Request For quote: Find where to buy TPS70345
Datasheet text preview:
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A AUGUST 2000 REVISED OCTOBER 2002
D Dual Output Voltages for Split-Supply D D D D D
Applications Selectable Power Up Sequencing for DSP Applications (See TPS704xx for Independent Enabling of Each Output) Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2 Fast Transient Response Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset With 120-ms Delay
D D D D D D D D D D
Open Drain Power Good for Regulator 1 Ultralow 185 µA (typ) Quiescent Current 2 µA Input Current During Standby Low Noise: 78 µVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 24-Pin PowerPAD TSSOP Package Thermal Shutdown Protection
PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
description
TPS703xx family of devices are designed to GND/HEATSINK VIN1 provide a complete power management solution VIN1 for TI DSP, processor power, ASIC, FPGA, and NC digital applications where dual output voltage MR2 regulators are required. Easy programmability of MR1 the sequencing function makes this family ideal EN for any TI DSP applications with power SEQ sequencing requirement. Differentiated features, GND such as accuracy, fast transient response, SVS VIN2 supervisory circuit (power on reset), manual reset VIN2 inputs, and enable function, provide a complete GND/HEATSINK system solution.
TPS70351 PWP 5V 0.22 µF VIN1 VOUT1 VSENSE1 PG1 VIN2 0.22 µF MR2 MR2 >2 V 2 V <0.7 V 22 µF 250 k PG1 3.3 V
GND/HEATSINK VOUT1 VOUT1 VSENSE1/FB1 NC PG1 RESET NC VSENSE2/FB2 VOUT2 VOUT2 GND/HEATSINK
NC No internal connection DSP
I/O
250 k RESET
>2 V
EN <0.7 V
EN
MR1 VSENSE2
SEQ
VOUT2 47 µF
1.8 V
Core
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A AUGUST 2000 REVISED OCTOBER 2002
description (continued)
The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1. The TPS703xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.
AVAILABLE OPTIONS TJ REGULATOR 1 VO (V) 3.3 V 3.3 V 40°C to 125°C to 125°C 3.3 V 3.3 V Adjustable (1.22 V to 5.5 V) REGULATOR 2 VO (V) 1.2 V 1.5 V 1.8 V 2.5 V Adjustable (1.22 V to 5.5 V) TSSOP (PWP) TPS70345PWP TPS70348PWP TPS70351PWP TPS70358PWP TPS70302PWP
NOTE: The TPS70302 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70302PWPR).
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A AUGUST 2000 REVISED OCTOBER 2002
detailed block diagram fixed voltage version
VIN1 (2 Pins) UVLO1 2.5 V GND Shutdown Current Sense 10 k ENA_1 VSENSE1 (see Note A) ENA_1 FB1 Vref UVLO1 FB1 0.95 × Vref Rising Edge Deglitch VIN1 PG1 VOUT1 (2 Pins)
Reference Thermal Shutdown Vref
+
Shutdown UV Comp FB2 0.83 × Vref FB1 0.83 × Vref UV Comp EN VIN1 2.5 V UVLO2 Current Sense Falling Edge Deglitch FB2 0.95 × Vref Power Sequence Logic ENA_1 ENA_2 Vref Rising Edge Deglitch Falling Edge Delay VIN1
MR2 RESET
Falling Edge Deglitch
FB2
MR1
+
ENA_2 ENA_2 10 k VOUT2(2 Pins) VSENSE2 (see Note A)
SEQ (see Note B) VIN2 (2 Pins)
NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. B. If the SEQ terminal is floating at the input, VOUT2 powers up first.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
Others parts begin by tp
TP-1 TP-2 TP-3 TP-4 TP-5 TP-6 TP-7 TP-8 TP-9 TP-10 TP-11 TP-12 TP-13 TP-14 TP-15 TP-16 TP-17 TP-18 TP-19 TP-20 TP-21 TP-22 TP-23 TP-24 TP-25 TP-26 TP-27 TP-28 TP-29 TP-30
|
|
|
