Details, datasheet, quote on part number: UCC3583Q
PartUCC3583Q
CategoryPower Management => PWM Power Supply => Post Regulation
TitlePost Regulation
Descriptionti UCC3583, Switch Mode Secondary Side Post Regulator
CompanyTexas Instruments, Inc.
DatasheetDownload UCC3583Q datasheet
Cross ref.Similar parts: UC2843A, UC2846, UC3846, UC3856
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Features, Applications

Switch Mode Secondary Side Post Regulator
FEATURES

Precision Secondary Side Post Regulation for Multiple Output Power Supplies Useful for Both Single Ended and Center Tapped Secondary Circuits Ideal Replacement for Complex Magnetic Amplifier Regulated Circuits Leading Edge Modulation Does Not Require Gate Drive Transformer High Frequency (>500kHz) Operation Applicable for Wide Range of Output Voltages High Current Gate Driver (0.5A Sink/1.5A Source) Average Current Limiting Loop

DESCRIPTION

The is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry. The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems. The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions. (continued)

VDD. 15V IVDD. 15mA RAMP. 0.3V to VDD + 1V IRAMP. 5mA IREF. 30mA PCOM. to 0.2V IGATE (twp < 1S and Duty Cycle to 1.8A ICOMP. to 5mA ICAO. to 5mA VSYNC. 0.6V to VREF +0.3V ISYNC. to 5mA INV, SS, ILIM, ISENSE. 0.3V to VREF + 0.3V Storage Temperature. to +150C Junction Temperature. to +150C Lead Temperature (Soldering, 10 sec.). +300C

All voltages are with respect to the COM terminal unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for to 125C for to 85C for UCC2583, and to 70C for UCC3583; VDD TA = TJ.

PARAMETER Ramp Generation and Synchronization Maximum Input Operating Frequency Ramp Frequency, Free Running Ramp Discharge Current Low Threshold Voltage High Threshold Voltage Synchronizing Threshold Voltage (On) Synchronizing Comparator Hysteresis Output Duty Cycle Minimum Duty Cycle Maximum Duty Cycle Output D/C = Output PW / Input PW Output D/C = Output PW / Input PW (Note 1) VRAMP 0.5V No min, no max, 0=TYP 3.75 For input with to 90% duty cycle (Note kHz mA TEST CONDITIONS MIN TYP MAX UNITS

UCC2583 UCC3583 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for to 125C for to 85C for UCC2583, and to 70C for UCC3583; VDD TA = TJ.

PARAMETER Voltage Error Amplifier VINV IINV VCOMP Low VCOMP High AVOL GBW Product Current Error Amplifier Input Offset Voltage Input CM Low Input CM High VCAO Low VCAO High Input Current (ILIM and CS Pins) AVOL GBW Product Soft Start Current UVLO VDD On Threshold Voltage VDD Off Threshold Voltage UVLO Hysteresis Bias Supply Clamp Voltage Supply Current (VDD) Output Driver VSAT High VSAT Low Rise Time Fall Time Reference VREF Line Regulation Load Regulation IREF 70C (UCC3583) IREF = 0, All Other Temperature Ranges VDD to 14V IREF V mV IGATE = 150mA IGATE = 50mA CGATE = 1nF CGATE = 100kHz With No Gate Output Load V No Load = 25C Common Mode for CS and ILIM (Note 1) Common Mode for CS and ILIM (Note 1) V+IN = 0V, VIN = 0.1V, ICAO = 100A V+IN = 0V, VIN = 0.1V, ICAO nA dB MHz A VCOMP = VINV, 70C (UCC3583) VCOMP = VINV, All Other Temperature Ranges VCOMP = VINV = 2.6V, ICOMP = 100A VINV = 2.4V, ICOMP 100A No Load = 25C (Note V dB MHz TEST CONDITIONS MIN TYP MAX UNITS


 

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