|Category||Semiconductors => Power Management => MOSFET and IGBT Gate Drivers => Low-side Driver|
|Part family||UCC37324 Dual 4 A Peak High Speed Low-Side Power MOSFET Drivers|
|Title||MOSFET and Power Drivers|
|Description||Dual 4 A Peak High Speed Low-Side Power MOSFET Drivers 8-SOIC 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download UCC37324D datasheet
|Cross ref.||Similar parts: 2EDN7524F, IR4426, IR4427, IRS2101, IRS2103, IRS2106, IRS2108, IRS2111, IRS21531DSPBF, IRS2153DSPBF|
|Operating Temperature Range(C)||0 to 70|
|Channel Input Logic||Non-Inverting|
|Approx. Price (US$)||0.75 | 1ku|
|Input Negative Voltage(V)||0|
|Number of Channels(#)||2|
|Features||Dual Non-inverting Outputs,Hysteretic Logic|
|Peak Output Current(A)||4|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Synchronous Rectifiers of a Current Doubler
Driving a current doubler synchronous rectification output stage can be a very complex task, especially for a phase shifted full bridge topology. However, using the A and B outputs of the UCC3895 along with the UCC37324 dual 4-A MOSFET driver, direct PWM c | Doc
|UCC3895EVM-001: UCC3895 Evaluation Module|
|UCCx895 and UCCx7324 Families PSpice Transient Model (Rev. A) - ZIP (01/27/2011)|
DUAL 4A PEAK HIGH SPEED LOW-SIDE POWER MOSFET DRIVERS
FEATURES D Industry-Standard Pin-Out D High Current Drive Capability A at the
Miller Plateau Region Efficient Constant Current Sourcing Using a Unique BiPolar & CMOS Output Stage TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times with 1.8-nF Load Typical Propagation Delay Times 25 ns with Input Falling and 35 ns with Input Rising to 15-V Supply Voltage Supply Current 0.3 mA Dual Outputs Can Be Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPADTM Package with 4.7°C/W jc Rated From to 85°C
APPLICATIONS D Switch Mode Power Supplies D DC/DC Converters D Motor Controllers D Line Drivers DESCRIPTION
The UCC37323/4/5 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads.Three standard logic options are offered dual-inverting, dual-noninverting and one-inverting and one-noninverting driver. The thermally enhanced 8-pin PowerPADTM MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. Using a design that inherently minimizes shoot-through current, these drivers deliver 4-A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.
PowerPADt is a trademark of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
OUTPUT CONFIGURATION TEMPERATURE RANGE to +85°C PACKAGED DEVICES SOIC-8 (D) UCC27325D MSOP-8 PowerPAD (DGN)} UCC27325DGN PDIP-8 (P) UCC37324P UCC27325PDual inverting D al nonIn Dual nonInverting erting One inverting, one noninverting
D (SOIC8) and DGN (PowerPADMSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27324DGNR) to order quantities of 2,500 devices per reel for or 1,000 devices per reel for DGN package. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. D, DGN, OR P PACKAGE (TOP VIEW)
PACKAGE SOIC-8 PDIP-8 MSOP PowerPAD-8 See Note 3 SUFFIX D P DGN jc (°C/W) 4.7 ja (°C/W) Power Rating (mW) = 70°C See Note 1 344655 See Note 500 1370 Derating Factor Above 70°C (mW/ C) See Note See Note 9 17.1
Notes: 1. 125°C operating junction temperature is used for power rating calculations 2. The range of values indicates the effect of pcboard. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pcboard where possible in order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made Easy, Texas Instruments Literature No. SLMA004. 3. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device.INPUTS (VIN_L, VIN_H) INA INB UCC37323 OUTA OUTB UCC37324 OUTA OUTB UCC37325 OUTA OUTB
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD. 16 V Output current (OUTA, OUTB) DC, IOUT_DC. 0.3 A Pulsed, (0.5 µs), IOUT_PULSED. 4.5 A. Power dissipation = 25°C (DGN package). W (D package). mW (P package). 350 mW Junction operating temperature, TJ. to 150°C Storage temperature, Tstg. to 150°C Lead temperature (soldering, 10 sec.),. 300°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.electrical characteristics, VDD TA = TJ, (unless otherwise noted) input (INA, INB)
PARAMETER VIN_H, logic 1 input threshold VIN_L, logic 0 input threshold Input current 0 V VIN VDD 10 0 TEST CONDITION MIN 1 10 TYP MAX UNITS V µA
PARAMETER Output current VOH, high-level output voltage VOL, low-level output level Output resistance high TEST CONDITION VDD 14 V, See Note 1, VOH = VDD VOUT, IOUT = 25°C, See Note TA = full range, See Note 3 Output resistance low = 25°C, See Note TA = full range See Note 3 Latch-up protection See Note 1 IOUT = 10 mA, IOUT = 10 mA, IOUT = 10 mA, IOUT = 10 mA, VDD 14 V, VDD 14 V, VDD 14 V, VDD 14 V, See Note 2 IOUT 10 mA MIN TYP MAX UNITS mV mA
NOTES: 1. Ensured by design. Not tested in production. 2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. 3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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