|Category||Interface and Interconnect|
|Description||Quad Fet Driver|
|Company||Texas Instruments, Inc.|
|Datasheet||Download UCC3776 datasheet
High Peak Output Current Each Output 1.5A Source, 2.0A Sink Wide Operating Voltage Range to 18V Thermal Shutdown CMOS Compatible Inputs Outputs Are Active Low for Undervoltage Lockout Condition
The is a four output BCDMOS buffer/driver designed to drive highly capacitive loads such as power MOSFET gates at high speeds. The device can be configured as either an inverting or non-inverting driver via the POL pin. The outputs are enabled by ENBL. When disabled, all outputs are active low. The device incorporates thermal shutdown with hysteresis for stability. The device also includes an undervoltage lockout circuit (UVLO) with hysteresis which disables the outputs when VDD is below a preset threshold. The outputs are held low during undervoltage lockout, even in the absence of VDD power to the device. This helps prevent MOSFET turn-on due to capacitive current through the gate-drain capacitance of the power MOSFET in the presence of high dV/dts. The logic input thresholds are compatible with standard 5V HCMOS logic.
Input Supply Voltage, VDD1, VDD2.20V Maximum DC Voltage Difference, VDD1 vs. VDD2.100mV Logic Input, IN1, IN4, ENBL Maximum forced + 0.3V Logic Inputs, IN2, IN3, POL Maximum forced + 0.3V Latch-up Protection withstand Reverse Current IREV, OUT3, OUT4.500mA Power Outputs, OUT3, OUT4 Maximum pulsed current (10% duty max, 10µsec max pulse width).3A Storage to +150°C Operating Junction to +150°C Lead Temperature (Soldering, 10 Seconds).300°C All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.DIL-16 (Top View) J, DP Packages PLCC-28 (Top View) Q Package
ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for to +125°C for to +85°C for to +70°C for UCC3776; VPOL = 5V, VENBL 4.5V < VDD TJ = TA.
PARAMETER Input Section VIH, Logic 1 Input Voltage VIL, Logic 0 Input Voltage IINn, Input Current ENBL Input Current POL Input Current TEST CONDITIONS MIN 3 VINn = 5V VINn = 0V VENBL = 5V VENBL = 0V VPOL = 5V VPOL = 0V TYP MAX UNITS V µA
UCC2776 UCC3776 ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated these specifications apply for to +125°C for to +85°C for to +70°C for UCC3776; VPOL = 5V, VENBL 4.5V < VDD TJ = TA.
PARAMETERTEST CONDITIONS Output Section VOH, High Output Voltage VOL, Low Output Voltage Output Resistance Output High Peak Current Output Low Peak Current UVLO Output Pull-down Voltage Switching Time Section Output Rise Time MIN IOUTn = 12V, VINn = 5V VDD - 1.0 IOUTn = 12V, VINn = 0V IOUTn = 12V, VINn = 12V, OUTn = 5V, VINn = 25°C (Note = 12V, OUTn = 5V, VINn = 25°C (Note = 3V, IOUTn = -10mA TYP MAX UNITS 1.5 V
COUTn = 1nF, VOUTn = 12V Output Fall Time COUTn = 1nF, VOUTn = 12V IN->OUT Delay Time (Rising Output) VINn = 2.5V, VOUTn = 0.1 VDD, = 12, COUTn = 0nF IN->OUT Delay Time (Falling Output) VINn = 2.5V, VOUTn = 0.9 VDD, = 12V, COUTn = 0nF Power Supply Section Power Supply Current = 0V, VENBL = 12V UVLO Threshold UVLO Hysteresis
ENBL: Logic level input to enable the drivers. When ENBL is low, the drivers outputs will be at GND potential, regardless of the status of POL. The input threshold is designed be 5 volt CMOS compatible, independent of the VDD voltage used on the device. There is a slight hysteresis in the input circuit to help reduce sensitivity to noise on the input signal or input ground. GND: Ground for the device, the supply return for the VDDs.There are four GND pads on the device. - IN4: Inputs to each driver (1-4). The input threshold is designed be 5 volt CMOS compatible, independent of the VDD voltage used on the device. There is a slight hysteresis in the input circuit to help reduce sensitivity to noise. - OUT4: Outputs to each driver (1-4). The outputs are totem pole DMOS circuits. In the absence of VDD on the device, the outputs will stay off, even with a capacitive displacement current into the output node. POL: Polarity selection for the drivers. A logic 0 selects inverting operation. A logic 1 selects non-inverting operation. The input threshold is designed be 5 volt CMOS compatible, independent of the VDD voltage used on the device. There is a slight hysteresis in the input circuit to help reduce sensitivity to noise. VDD1: Supply Voltage for drivers 1 and 4. Tied internally VDD2. VDD2: Supply Voltage for drivers 2 and 3. Tied internally to VDD1.
Figure 1 depicts a block diagram of the UCC3776 Quad FET Driver. Four high current, high speed gate drivers with CMOS compatible input stages are provided. Polarity select and enable inputs provide circuit integration flexibility, while power packaging and high speed drive circuitry allow for driving high power MOSFET gates in high speed applications.
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