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Part: UCC3809-2
Category:
Analog & Mixed-Signal Processing
-> Power
Description: Economy Primary Side Controller
Company: Texas Instruments, Inc.
Datasheet: Download UCC3809-2 datasheet File size : 375 kB
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Datasheet text preview:
application INFO available
UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2
Economy Primary Side Controller
FEATURES
· User Programmable Soft Start With Active Low Shutdown · User Programmable Maximum Duty Cycle · Accessible 5V Reference · Undervoltage Lockout · Operation to 1MHz · 0.4A Source/0.8A Sink FET Driver · Low 100µA Startup Current
DESCRIPTION
The UCC3809 family of BCDMOS economy low power integrated circuits contains all the control and drive circuitry required for off-line and isolated DC-to-DC fixed frequency current mode switching power supplies with minimal external parts count. Internally implemented circuits include undervoltage lockout featuring startup current less than 100µA, a user accessible voltage reference, logic to ensure latched operation, a PWM comparator, and a totem pole output stage to sink or source peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state. Oscillator frequency and maximum duty cycle are programmed with two resistors and a capacitor. The UCC3809 family also features full cycle soft start. The family has UVLO thresholds and hysteresis levels for off-line and DC-to-DC systems as shown in the table to the left.
PART TURN ON TURN OFF NUMBER THRESHOLD THRESHOLD UCCX809-1 10V 8V UCCX809-2 15V 8V
The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP (N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and MSOP packages make the device ideal for applications where board space and height are at a premium.
TYPICAL APPLICATION DIAGRAM
R ST ART
V IN
FB
1V
1
1V
NOISE FIL TER
FEED BAC K
R EF
+5V
SS
5V R EF
8
C REF
VOUT
6 µA
2
C U R R EN T SEN SE
SLOPE C OM P
0.5V
C SS
DISABLE
U VL O
VD D
7
15/8V 10/8V
17.5V
C VDD
R T1
3
OSC
4
CT
PWM L A TC H CLK
R Q S
6
OU T
R T2
GN D
5
V REF
UDG-99036
SLUS166A - NOVEMBER 1999
UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA IOUT (tpw < 1µs and Duty Cycle < 10%) . . . . . . . . 0.4A to 0.8A RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . 0.3V to REF + 0.3V IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . 55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
CONNECTION DIAGRAM
SOIC-8, DIL-8 (Top View) D, N and J Packages
* Values beyond which damage may occur. All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
TSSOP-8 (Top View) PW Package
1 2 3 4 FB SS RT1 RT2 REF VDD OUT GND 8 7 6 5
MSOP-8 (Top View) P Package
1 2 3 4 FB SS RT1 RT2 REF VDD OUT GND 8 7 6 5
ORDERING INFORMATION
UCC1809-X UCC2809-X UCC3809-X Temperature Range Available Packages 55°C to +125°C J 40°C to +85°C N, D, P, PW 0°C to +70°C N, D, P, PW
UCC 809
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.
PARAMETER Supply Section VDD Clamp IVDD IVDD Starting Undervoltage Lockout Section Start Threshold (UCCx809-1) UVLO Hysteresis (UCCx809-1) Start Threshold (UCCx809-2) UVLO Hysteresis (UCCx809-2) Voltage Reference Section Output Voltage Line Regulation Load Regulation Comparator Section IFB Comparator Threshold OUT Propagation Delay (No Load) TEST CONDITIONS IVDD = 10mA No Load MIN 16 TYP 17.5 600 MAX 19 900 100 10.4 15.6 UNIT V µA µA V V V V V mV mV nA V ns
9.4 1.65 14.0 6.2 IREF = 0mA VDD = 10V to 15V IREF = 0mA to 5mA Output Off 0.9 VFB = 0.8V to 1.2V at TR = 10ns 4.75 5 2 2 100 0.95 50
5.25
1 100
2
UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. TA = TJ.
PARAMETER Soft Start Section ISS VSS Low Shutdown Threshold Oscillator Section Frequency Frequency Change with Voltage CT Peak Voltage CT Valley Voltage CT Peak to Peak Voltage Output Section Output VSAT Low Output VSAT High Output Low Voltage During UVLO Minimum Duty Cycle Maximum Duty Cycle Rise Time Fall Time TEST CONDITIONS VDD = 16V, VSS = 0V; 40°C to +85°C VDD = 16V, VSS = 0V; +85°C VDD = 7.5V, ISS = 200µA MIN 4.9 4.0 0.44 RT1 = 10k, RT2 = 4.32k, CT = 820pF VDD = 10V to 15V 90 TYP 7.0 7.0 0.48 100 0.1 3.33 1.67 1.67 0.8 0.8 0 70 35 18 MAX 9.1 10.0 0.2 0.52 110 UNIT µA µA V V kHz %/V V V V V V V % % ns ns
1.54 IOUT = 80mA (dc) IOUT = 40mA (dc), VDD OUT IOUT = 20mA (dc) VFB = 2V COUT = 1nF COUT = 1nF
1.80 1.5 1.5 1.5
PIN DESCRIPTIONS
FB: This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250 on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND. GND: Reference ground and power ground for all functions. OUT: This pin is the high current power driver output. A minimum series gate resistor of 3.9 is recommended to limit the gate drive current when operating with high bias voltages. REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47µF ceramic capacitor. RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.74 · (CT + 27pF) · RT1). The positive threshold of the internal oscillator is sensed through inactive timing resistor RT2 which connects to pin RT2 and timing capacitor CT. 3 RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.74 · (CT + 27pF) · RT2). The negative threshold of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor CT. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6µA current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and IVDD < 100µA. VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor.
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