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Details, datasheet, quote on part number:VSP2230Y/2K
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| Part: | VSP2230Y/2K |
| Category: | Multimedia => Video => Imaging => CCD Imaging Analog Front Ends |
| Description: | ti VSP2230, 10-Bit, 36Msps CCD Signal Processor For Digital Cameras |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download VSP2230Y/2K datasheet File size : 231 kB |
| Request For quote: | Find where to buy VSP2230Y/2K
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Datasheet text preview:
VSP2230
SLAS319 MAY 2001
CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS
FEATURES D CCD Signal Processing D D D D
Correlated Double Sampling (CDS) Programmable Black Level Clamping Programmable Gain Amplifier (PGA) 6-dB to 42-dB Gain Ranging 10-Bit Digital Data Output Up to 36-MHz Conversion Rate No Missing Codes 76-dB Signal-to-Noise Ratio Portable Operation Low Voltage: 2.7 V to 3.6 V Low Power: 120 mW (typ) at 3.0 V Standby Mode: 6 mW
DESCRIPTION
The VSP2230 is a complete mixed-signal processing IC for digital cameras that provides signal conditioning and analog-to-digital conversion for the output of a CCD array. The primary CCD channel provides correlated double sampling (CDS) to extract the video information from the pixels, a 6-dB to 42-dB gain with digital control for varying illumination conditions, and black level clamping for an accurate black level reference. Input signal clamping and offset correction of the input CDS is also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The VSP2230Y is pin-to-pin compatible with the VSP2260Y (10 bit, 20 MHz) one-chip product. The VSP2230Y is available in a 48-pin LQFP package and operates from a single 3-V/3.3-V supply.
VSP2230 block diagram
CLPDM SHP SHD SLOAD SCLK SDATA RESET ADCCK DRVDD VCC
Serial Interface Input Clamp Timing Control B(09) Analog-to-Digital Converter Output Latch 10-Bit Digital Output
CCDIN
Correlated Double Sampling (CDS)
Programmable Gain Amplifier 6 to 42 dB (PGA)
CCD Output Signal
Preblanking
Optical Black (OB) Level Clamping
Reference Voltage Generator
PBLK
COB
CPLOB
BYPP2 BYP BYPM REFN CM
REFP
DRVGND
GNDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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VSP2230
SLAS319 MAY 2001
PACKAGE/ORDERING INFORMATION PRODUCT VSP2230Y VSP2230Y PACKAGE 48-pin LQFP 48-pin LQFP PACKAGE OUTLINE NUMBER ZZ340 ZZ340 SPECIFIED TEMPERATURE RANGE 0_C to 85_C 0_C to 85_C PACKAGE MARKING VSP2230Y VSP2230Y ORDERING NUMBER VSP2230Y VSP2230Y/2K TRANSPORT MEDIA 250 pcs. Tray
Tape and Reel This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., VSP2230CDR). DEMO BOARD ORDERING INFORMATION PRODUCT VSP2230Y ORDERING NUMBER DEM-VSP2230Y
pin assignments
48-PIN LQFP PACKAGE (TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
CCDIN BYPP2 COB VCC GNDA GNDA
GNDA GNDA VCC VCC BYPM BYP
CM REFP REFN VCC GNDA GNDA NC NC RESET SLOAD SDATA SCLK
37 38 39 40 41 42 43 44 45 46 47 48 1 234 567 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLPDM SHD SHP CLPOB PBLK VCC GNDA ADCCK GNDA DRVGND DRVDD
NC No internal connection
2
NC NC B0(LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9(MSB)
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VSP2230
SLAS319 MAY 2001
Terminal Functions
TERMINAL NAME ADCCK B0(LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9(MSB) BYP BYPM BYPP2 CCDIN CLPDM CLPOB CM COB DRVDD DRVGND GNDA NC PBLK NO. 16 3 4 5 6 7 8 9 10 11 12 31 32 29 30 23 20 37 28 13 14 15, 17, 25, 26, 35, 36, 41, 42 1, 2, 43, 44 19 DI TYPE DI DO DO DO DO DO DO DO DO DO DO AO AO AO AI DI DI AO AO P P P Master clock, See Note 1 A/D converter output, Bit 0 (LSB) A/D converter output, Bit 1 A/D converter output, Bit 2 A/D converter output, Bit 3 A/D converter output, Bit 4 A/D converter output, Bit 5 A/D converter output, Bit 6 A/D converter output, Bit 7 A/D converter output, Bit 8 A/D converter output, Bit 9 (MSB) Internal reference C (bypass to ground), See Note 2 Internal reference N (bypass to ground), See Note 3 Internal reference P (bypass to ground), See Note 3 CCD signal input Dummy pixel clamp pulse (Default = Active Low), See Note 4 Optical black clamp pulse (Default = Active Low), See Note 4 A/D converter common mode voltage (bypass to ground), See Note 2 Optical black clamp loop reference (bypass to ground), See Note 5 Power supply. Exclusively for digital output Digital ground. Exclusively for digital output Analog ground Should be left open Preblanking High = Normal operation mode Low = Preblanking mode: digital output all zero A/D converter negative reference (bypass to ground), See Note 2 A/D converter positive reference (bypass to ground), See Note 2 Asynchronous system reset (active low) Clock for serial data shift (triggered at the rising edge) Serial data input CDS reference level sampling pulse (Default = Active Low), See Note 4 CDS Data level sampling pulse (Default = Active Low), See Note 4 Serial data latch signal (triggered at the rising edge) Analog power supply DESCRIPTION
REFN REFP RESET SCLK SDATA SHP SHD SLOAD VCC
39 38 45 48 47 21 22 46 18, 24, 27, 33, 34, 40
AO AO DI DI DI DI DI DI P
Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output NOTES: 1. There are two options to drive the A/D converter: a). External drive mode. The master clock (ADCCK) drives A/D converter directly. b). Internal drive mode. The clock internally generated by on-chip timing control circuit using SHP and SHD signals drives A/D converter. 2. BYP, CM, REFN, and REFP should be connected to ground using a bypass capacitor (0.1 µF). Refer to voltage reference for details. 3. BYPM, BYPP2 should be connected to ground using a bypass capacitor with a recommend value of 200 pF to 600 pF. However, this depends on the application environment. Refer to voltage reference for details. 4. Refer to serial interface for details. 5. COB should be connected to ground using a bypass capacitor with a recommend value of 0.1 µF to 0.22 µF. However, this depends on the application environment. Refer to optical black level clamp loop for details.
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