|
Details, datasheet, quote on part number:VSP2260
| |
Datasheet text preview:
VSP2260
VSP 226 0
www.ti.com
CCD SIGNAL PROCESSOR for DIGITAL CAMERAS
FEATURES
q CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping q PROGRAMMABLE GAIN AMPLIFIER (PGA): 6dB to +42dB Gain Ranging q 10-BIT DIGITAL DATA OUTPUT: Up to 20MHz Conversion Rate No Missing Codes q 79dB SIGNAL-TO-NOISE RATIO q PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 83mW (typ) at 3.0V Stand-By Mode: 6mW
CLPDM SHP SHD SLOAD SCLK SDATA
DESCRIPTION
The VSP2260 is a complete mixed-signal processing IC for digital cameras, providing signal conditioning and Analog-to-Digital (A/D) conversion for the output of a CCD array. The primary CCD channel provides Correlated Double Sampling (CDS) to extract video information from the pixels, 6dB to +42dB gain range with digital control for varying illumination conditions, and black level clamping for an accurate black level reference. Input signal clamping and offset correction of the input CDS are also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The VSP2260Y is available in an LQFP-48 package and operates from a single +3V/+3.3V supply.
RESET ADCCK DRVDD VCC
Serial Interface Input Clamp Timing Control
CCDIN
Correlated Double Sampling (CDS)
Programmable Gain Amplifier (PGA)
6dB to +42dB
AnalogtoDigital Converter
Output Latch
10-Bit Digital Output
B[9:0]
CCD Output Signal
Preblanking
Optical Black (OB) Level Clamping
Reference Voltage Generator
PBLK
COB
CLPOB
BYPP2
BYP
BYPM
REFN
CM
REFP
DRVGND
GNDA
Copyright © 2000, Texas Instruments Incorporated
SBMS010
Printed in U.S.A. November, 2000
SPECIFICATIONS
At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (fADCCK) = 20MHz, unless otherwise noted. VSP2260Y PARAMETER RESOLUTION CONVERSION RATE DIGITAL INPUT Logic Family Input Voltage Input Current DIGITAL OUTPUT Logic Family Logic Coding Output Voltage ADCCK Clock Duty Cycle Input Capacitance Maximum Input Voltage ANALOG INPUT (CCDIN) Input Signal Level for Full-Scale Out Input Capitance Input Limit TRANSFER CHARACTERISTICS Differential Non-Linearity (DNL) Integral Non-Linearity (INL) No Missing Codes Step Response Settling Time Overload Recovery Time Data Latency Signal-to-Noise Ratio(1) CCD Offset Correction Range CDS Reference Sample Settling Time Data Sample Settling Time INPUT CLAMP Clamp-On Resistance Clamp Level PROGRAMMABLE GAIN AMP (PGA) Gain-Control Resolution Maximum Gain High Gain Medium Gain Low Gain Minimum Gain Gain Control Error OPTICAL BLACK CLAMP LOOP Control DAC Resolution Optical Black Clamp Level Min Output Current for Control DAC Max Output Current for Control DAC Loop Time Constant Slew Rate CCOB REFERENCE Positive Reference Voltage Negative Reference Voltage POWER SUPPLY Supply Voltage Power Dissipation TEMPERATURE RANGE Operating Temperature Thermal Resistance VCC, DRVDD 2.7 Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended Stand-By Mode: fADCCK = Not Apply 25 Within 1LSB, Driver Impedance = 50 Within 1LSB, Driver Impedance = 50 400 1.5 10 42 34 20 0 6 ±0.5 10 Programmable Range of Clamp Level OBCLP Level at CODE = 1000 COB Pin COB Pin CCOB = 0.1µF = 0.1µF, Output Current from Control DAC is Saturated 0 32 ±0.15 ±153 40.7 1530 1.75 1.25 3.0 83 6 3.6 60 PGA Gain = 0dB 20 TTL 1.7 1.0 ±20 ±20 CMOS Straight Binary Logic HIGH (VOH) IOH = 2mA Logic LOW (VOL) IOL = 2mA 2.4 0.4 50 5 0.3 900 15 0.3 PGA Gain = 0dB PGA Gain = 0dB Full-Scale Step Input Step Input from 1.8V to 0V Grounded Input Cap, PGA Gain = 0dB Grounded Input Cap, Gain = +24dB 180 ±0.5 ±1 Guaranteed 1 2 9 (Fixed) 79 55 200 11 11 3.3 5.3 V V % pF V mV pF V LSB LSB Pixel Pixels Clock Cycles dB dB mV ns ns V Bits dB dB dB dB dB dB Bits LSB LSB µA µA µs V/s V V V mW mW °C °C/W CONDITIONS MIN TYP 10 MAX UNITS Bits MHz
LOW to HIGH Threshold Voltage (VT+) HIGH to LOW Threshold Voltage (VT) Logic HIGH (IIH) VIN = +3V Logic LOW (IIL) VIN = 0V
V V µA µA
Gain Gain Gain Gain Gain
Code Code Code Code Code
= = = = =
1111111111 1101001000 1000100000 0010000000 0000000000
+85 100
JA
LQFP-48
NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).
2
VSP2260
SBMS010
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage: VCC, DRVDD .. +4.0V Supply-Voltage Differences: Among VCC ........ ±0.1V Ground-Voltage Differences: Among GNDA ... ±0.1V Digital Input Voltage ... 0.3 to +5.3V Analog Input Voltage ........ 0.3 to VCC + 0.3V Input Current (Any Pins Except Supplies) .... ±10mA Ambient Temperature Under Bias .... 40 to +125°C Storage Temperature ......... 55 to +125°C Junction Temperature ........... +150°C Lead Temperature (Soldering, 5s) ...... +260°C Package Temperature (IR Reflow, Peak, 10s) ..... +235°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 340 SPECIFIED TEMPERATURE RANGE 0 to +85°C PACKAGE MARKING VSP2260Y ORDERING NUMBER(1) VSP2260Y VSP2260Y/2K TRANSPORT MEDIA 250-Piece Tray Tape and Reel
PRODUCT VSP2260Y
PACKAGE LQFP-48
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "VSP2260Y/2K" will get a single 2000 piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT VSP2260Y ORDERING NUMBER DEM-VSP2260Y
VSP2260
SBMS010
3
|
|
