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Details, datasheet, quote on part number:VSP2262Y/2K
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| Part: | VSP2262Y/2K |
| Category: | Multimedia => Video => Imaging => CCD Imaging Analog Front Ends |
| Description: | ti VSP2262, 12-Bit, 20Msps CCD Signal Processor For Digital Cameras |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download VSP2262Y/2K datasheet File size : 224 kB |
| Request For quote: | Find where to buy VSP2262Y/2K
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Datasheet text preview:
VSP2262
VSP 226 2
www.ti.com
CCD SIGNAL PROCESSOR for DIGITAL CAMERAS
FEATURES
q CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping q PROGRAMMABLE GAIN AMPLIFIER (PGA): 6dB to +42dB Gain Ranging q 12-BIT DIGITAL DATA OUTPUT: Up to 20MHz Conversion Rate No Missing Codes q 79dB SIGNAL-TO-NOISE RATIO q PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 83mW (typ) at 3.0V Stand-By Mode: 6mW
DESCRIPTION
The VSP2262 is a complete mixed-signal processing IC for digital cameras, providing signal conditioning and Analog-to-Digital (A/D) conversion for the output of a CCD array. The primary CCD channel provides Correlated Double Sampling (CDS) to extract video information from the pixels, 6dB to +42dB gain range with digital control for varying illumination conditions, and black level clamping for an accurate black level reference. Input signal clamping and offset correction of the input CDS are also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The VSP2262Y is available in an LQFP-48 package and operates from a single +3V/+3.3V supply.
CLPDM
SHP SHD
SLOAD SCLK SDATA
RESET
ADCCK
DRVDD
VCC
Serial Interface Input Clamp Timing Control
CCDIN
Correlated Double Sampling (CDS)
Programmable Gain Amplifier (PGA)
6dB to +42dB
AnalogtoDigital Converter
Output Latch
12-Bit Digital Output
B[11:0]
CCD Output Signal
Preblanking
Optical Black (OB) Level Clamping
Reference Voltage Generator
PBLK
COB
CLPOB
BYPP2
BYP
BYPM
REFN
CM
REFP
DRVGND
GNDA
Copyright © 2000, Texas Instruments Incorporated
SBMS011
Printed in U.S.A. November, 2000
SPECIFICATIONS
At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (fADCCK) = 20MHz, unless otherwise noted. VSP2262Y PARAMETER RESOLUTION CONVERSION RATE DIGITAL INPUT Logic Family Input Voltage Input Current DIGITAL OUTPUT Logic Family Logic Coding Output Voltage ADCCK Clock Duty Cycle Input Capacitance Maximum Input Voltage ANALOG INPUT (CCDIN) Input Signal Level for Full-Scale Out Input Capitance Input Limit TRANSFER CHARACTERISTICS Differential Non-Linearity (DNL) Integral Non-Linearity (INL) No Missing Codes Step Response Settling Time Overload Recovery Time Data Latency Signal-to-Noise Ratio(1) CCD Offset Correction Range CDS Reference Sample Settling Time Data Sample Settling Time INPUT CLAMP Clamp-On Resistance Clamp Level PROGRAMMABLE GAIN AMP (PGA) Gain-Control Resolution Maximum Gain High Gain Medium Gain Low Gain Minimum Gain Gain Control Error OPTICAL BLACK CLAMP LOOP Control DAC Resolution Optical Black Clamp Level Min Output Current for Control DAC Max Output Current for Control DAC Loop Time Constant Slew Rate CCOB REFERENCE Positive Reference Voltage Negative Reference Voltage POWER SUPPLY Supply Voltage Power Dissipation TEMPERATURE RANGE Operating Temperature Thermal Resistance VCC, DRVDD 2.7 Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended Stand-By Mode: fADCCK = Not Apply 25 Within 1LSB, Driver Impedance = 50 Within 1LSB, Driver Impedance = 50 400 1.5 10 42 34 20 0 6 ±0.5 10 Programmable Range of Clamp Level OBCLP Level at CODE = 1000 COB Pin COB Pin CCOB = 0.1µF = 0.1µF, Output Current from Control DAC is Saturated 2 130 ±0.15 ±153 1530 1.75 1.25 3.0 86 6 3.6 60 PGA Gain = 0dB 20 TTL 1.7 1.0 ±20 ±20 CMOS Straight Binary Logic HIGH (VOH) IOH = 2mA Logic LOW (VOL) IOL = 2mA 2.4 0.4 50 5 0.3 900 15 0.3 PGA Gain = 0dB PGA Gain = 0dB Full-Scale Step Input Step Input from 1.8V to 0V Grounded Input Cap, PGA Gain = 0dB Grounded Input Cap, Gain = +24dB 180 ±0.5 ±1 Guaranteed 1 2 9 (Fixed) 79 55 200 11 11 3.3 5.3 V V % pF V mV pF V LSB LSB Pixel Pixels Clock Cycles dB dB mV ns ns V Bits dB dB dB dB dB dB Bits LSB LSB µA µA µs V/s V V V mW mW °C °C/W CONDITIONS MIN TYP 12 MAX UNITS Bits MHz
LOW to HIGH Threshold Voltage (VT+) HIGH to LOW Threshold Voltage (VT) Logic HIGH (IIH) VIN = +3V Logic LOW (IIL) VIN = 0V
V V µA µA
Gain Gain Gain Gain Gain
Code Code Code Code Code
= = = = =
1111111111 1101001000 1000100000 0010000000 0000000000
+85 100
JA
LQFP-48
NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).
2
VSP2262
SBMS011
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage: VCC, DRVDD .. +4.0V Supply-Voltage Differences: Among VCC ........ ±0.1V Ground-Voltage Differences: Among GNDA ... ±0.1V Digital Input Voltage ... 0.3 to +5.3V Analog Input Voltage ........ 0.3 to VCC + 0.3V Input Current (Any Pins Except Supplies) .... ±10mA Ambient Temperature Under Bias .... 40 to +125°C Storage Temperature ......... 55 to +125°C Junction Temperature ........... +150°C Lead Temperature (Soldering, 5s) ...... +260°C Package Temperature (IR Reflow, Peak, 10s) ..... +235°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 340 SPECIFIED TEMPERATURE RANGE 0 to +85°C PACKAGE MARKING VSP2262Y ORDERING NUMBER(1) VSP2262Y VSP2262Y/2K TRANSPORT MEDIA 250-Piece Tray Tape and Reel
PRODUCT VSP2262Y
PACKAGE LQFP-48
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "VSP2262Y/2K" will get a single 2000 piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT VSP2262Y ORDERING NUMBER DEM-VSP2262Y
VSP2262
SBMS011
3
PIN CONFIGURATION
Top View
BYPP2 CCDIN GNDA GNDA GNDA GNDA BYPM COB BYP VCC VCC VCC
LQFP
36 CM 37 REFP 38 REFN 39 VCC 40 GNDA 41 GNDA 42 NC 43 NC 44 RESET 45 SLOAD 46 SDATA 47 SCLK 48 1
B0 (LSB)
35
34
33
32
31
30
29
28
27
26
25 24 VCC 23 CLPDM 22 SHD 21 SHP 20 CLPOB 19 PBLK
VSP2262
18 VCC 17 GNDA 16 ADCCK 15 GNDA 14 DRVGND 13 DRVDD
2
B1
3
B2
4
B3
5
B4
6
B5
7
B6
8
B7
9
B8
10
B9
11
B10
12
B11 (MSB)
PIN DESCRIPTIONS
PIN NAME TYPE(1) DESCRIPTION DO DO DO DO DO DO DO DO DO DO DO DO P P P DI P P DI Bit 0 (LSB), A/D Converter Output Bit 1, A/D Converter Output Bit 2, A/D Converter Output Bit 3, A/D Converter Output Bit 4, A/D Converter Output Bit 5, A/D Converter Output Bit 6, A/D Converter Output Bit 7, A/D Converter Output Bit 8, A/D Converter Output Bit 9, A/D Converter Output Bit 10, A/D Converter Output Bit 11 (MSB), A/D Converter Output Power Supply, Exclusively for Digital Output Digital Ground, Exclusively for Digital Output Analog Ground Clock for Digital Output Buffer Analog Ground Analog Power Supply Preblanking: HIGH = Normal Operation Mode LOW = Preblanking Mode: Digital Output "All Zero" Optical Black Clamp Pulse (Default = Active LOW) (5) CDS Reference Level Sampling Pulse (Default = Active LOW)(5) CDS Data Level Sampling Pulse (Default = Active LOW) (5) Dummy Pixel Clamp Pulse (Default = Active LOW)(5) PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME VCC GNDA GNDA VCC COB BYPP2 CCDIN BYP BYPM VCC VCC GNDA GNDA CM REFP REFN VCC GNDA GNDA NC NC RESET SLOAD SDATA SCLK TYPE(1) DESCRIPTION P P P P AO AO AI AO AO P P P P AO AO AO P P P DI DI DI DI Analog Power Supply Analog Ground Analog Ground Analog Power Supply Optical Black Clamp Loop Reference(2) Internal Reference P(3) CCD Signal Input Internal Reference C(4) Internal Reference N(3) Analog Power Supply Analog Power Supply Analog Ground Analog Ground A/D Converter Common-Mode Voltage(4) A/D Converter Positive Reference(4) A/D Converter Negative Reference(4) Analog Power Supply Analog Ground Analog Ground Should be Left OPEN Should be Left OPEN Asynchronous System Reset (Active LOW) Serial Data Latch Signal (Triggered at the Rising Edge) Serial Data Input Clock for Serial Data Shift (Triggered at the Rising Edge) 1 B0 (LSB) 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 B9 11 B10 12 B11 (MSB) 13 DRVDD 14 DRVGND 15 GNDA 16 ADCCK 17 GNDA 18 VCC 19 PBLK
20 21 22 23
CLPOB SHP SHD CLPDM
DI DI DI DI
NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the "Optical Black Level Clamp Loop" section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 400pF to 9000pF, however, it depends on the application environment. Refer to the "Voltage Reference" section for more detail. (4) Should be connected to ground with a bypass capacitor (0.1µF). Refer to the "Voltage Reference" section for more detail. (5) Refer to "Serial Interface" section for more detail.
4
VSP2262
SBMS011
CDS TIMING SPECIFICATIONS
CCD Output Signal
N
N+1
N+2
N+3
tWP
tCKP
SHP(1)
tPD
tDP tWD
tS tCKP
SHD(1) tS tINHIBIT tADC tADC tCKP
ADCCK
tHOLD
tOD
B[11:0]
N 11
N 10
N9
N8
N7
SYMBOL tCKP tADC t WP tWD tPD tDP tS tINHIBIT tHOLD tOD DL
PARAMETER Clock Period ADCCK HIGH/LOW Pulse Width SHP Pulse Width SHD Pulse Width SHP Trailing Edge to SHD Leading Edge(1) SHD Trailing Edge to SHP Leading Edge(1) Sampling Delay Inhibited Clock Period Output Hold Time Output Delay Data Latency, Normal Operation Mode
MIN 48 20 14 11 8 12
TYP
MAX
UNITS ns ns ns ns ns ns
5 20 7 38 9 (fixed)
ns ns ns ns Clock Cycles
NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). The user can select the active polarity (Active LOW or Active HIGH) through the serial interface. Refer to the "Serial Interface" section for more detail.
VSP2262
SBMS011
5
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